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-- Company: 
-- Engineer:
--
-- Create Date:    07:53:41 10/28/05
-- Design Name:    
-- Module Name:    parity_bitser - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity parity_bitser is
    Port ( rst : in std_logic;
           clk : in std_logic;
           srst : in std_logic;
           ce : in std_logic;
           d_in : in std_logic;
           parity : out std_logic);
end parity_bitser;

architecture Behavioral of parity_bitser is

signal parity_i : std_logic;

begin

process (rst, srst, clk, ce, d_in) 
begin
   if rst='1' then 
      parity_i <= '1';
   elsif clk='1' and clk'event then
	   if srst='1' then 
   	   parity_i <= '1';
      elsif ce = '1' and d_in = '1' then
          parity_i <= not parity_i;
		end if;
   end if;
end process;

parity <= parity_i;

end Behavioral;