jens d908ae0e9e - SDRAM can now operate at different speed than BUS clock ...

- separated bus-clock (sys_clk) and SDRAM-clocks
  - added async. FIFOs for clock domain separation
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@578 cc03376c-175c-47c8-b038-4cd826a8556b

2009-11-03 20:42:27 +00:00

..

ddr_phy_virtex4.vhd

- Removed read data mask

2008-10-14 17:07:48 +00:00

mt46v16m16.vhd

Intital revision

2008-10-02 13:37:55 +00:00

reset_virtex4.vhd

Intital revision

2008-10-02 13:37:55 +00:00

sdram_cmd.vhd

Minor changes

2008-10-18 11:36:33 +00:00

sdram_config.vhd

- using now 64-bit SDR interface (2 SDRAMS)

2008-10-18 11:37:01 +00:00

sdram_ctrl_frontend64_wb.vhd

- SDRAM can now operate at different speed than BUS clock

2009-11-03 20:42:27 +00:00

sdram_ctrl_frontend_wb.vhd

- SDRAM can now operate at different speed than BUS clock

2009-11-03 20:42:27 +00:00

sdram_ctrl_top.vhd

- SDRAM can now operate at different speed than BUS clock

2009-11-03 20:42:27 +00:00

sdram_ctrl.vhd

- introduced per-bank activation (avoids multiple activations on same bank)

2008-10-18 11:36:07 +00:00

sdram_types.vhd

Intital revision

2008-10-02 13:37:55 +00:00

tb_sdram_ctrl_frontend64_wb.vhd

- SDRAM can now operate at different speed than BUS clock

2009-11-03 20:42:27 +00:00

tb_sdram_ctrl_frontend_wb.vhd

- SDRAM can now operate at different speed than BUS clock

2009-11-03 20:42:27 +00:00