jens 7f8a82d9ba - added asynchronous BUS FIFOs ...

- added cpu_clk
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git-svn-id: http://moon:8086/svn/vhdl/trunk@724 cc03376c-175c-47c8-b038-4cd826a8556b

2010-02-07 19:01:33 +00:00

..

.directory_history

- renamed bui, icache and dcache

2009-01-23 20:29:14 +00:00

dcache.vhd

Minor changes

2010-02-06 13:16:05 +00:00

icache.vhd

- removed unused 'en' pin.

2009-11-24 11:30:36 +00:00

mips_alu.vhd

Initial import

2008-08-23 07:19:47 +00:00

mips_bcu.vhd

Removed zero check

2008-09-20 21:44:03 +00:00

mips_bui.vhd

- added asynchronous BUS FIFOs

2010-02-07 19:01:33 +00:00

mips_cop.vhd

- added some comments

2009-10-17 17:33:45 +00:00

mips_instr.vhd

- added instructions 'lwcz' and 'swcz'.

2009-03-18 22:40:33 +00:00

mips_muldiv.vhd

Initial import

2008-08-23 07:19:47 +00:00

mips_pipeline.vhd

- Bugfix: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect.

2009-10-17 12:58:28 +00:00

mips_reg.vhd

- removed RAM-init during synthesizing

2009-02-08 17:32:41 +00:00

mips_shifter.vhd

Bugfix in gen_fill_mask_rom (wrong result on zero shift amounts due to width mismatch)

2009-10-14 21:15:31 +00:00

mips_top.vhd

- added asynchronous BUS FIFOs

2010-02-07 19:01:33 +00:00

mips_types.vhd

- added pin non-maskable interrupt (NMI).

2009-10-03 16:41:26 +00:00