jens
ea60299d26
git-svn-id: http://moon:8086/svn/vhdl/trunk@1414 cc03376c-175c-47c8-b038-4cd826a8556b
108 lines
2.8 KiB
VHDL
108 lines
2.8 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: cpu_embedded using cpu_core and rom
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-- Copyright (C) 2007 J. Ahrensfeld
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-- This library is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- This library is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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-- For questions and ideas, please contact the author at jens@jayfield.org
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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use work.cpu_pkg.all;
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entity cpu_embedded is
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Port (
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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int_in : in STD_LOGIC;
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int_ack : out STD_LOGIC;
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xmem_we : out STD_LOGIC;
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xmem_re : out STD_LOGIC;
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xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0);
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xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
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xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
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io_sel : out STD_LOGIC
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);
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end cpu_embedded;
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architecture rtl of cpu_embedded is
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signal rom_data : unsigned (IMEM_DATA_WIDTH-1 downto 0);
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signal rom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0);
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COMPONENT cpu
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Port (
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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int_in : in STD_LOGIC;
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int_ack : out STD_LOGIC;
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xmem_we : out STD_LOGIC;
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xmem_re : out STD_LOGIC;
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instr_din : in unsigned (IMEM_DATA_WIDTH-1 downto 0);
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instr_addr : out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
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xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0);
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xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
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xmem_addr : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
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io_sel : out STD_LOGIC
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);
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END COMPONENT;
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COMPONENT irom
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Port (
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clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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addr : in inst_addr_t;
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dout : out inst_t
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);
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END COMPONENT;
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begin
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inst_cpu: cpu
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PORT MAP(
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rst => rst,
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clk => clk,
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ce => ce,
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int_in => int_in,
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int_ack => int_ack,
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xmem_we => xmem_we,
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xmem_re => xmem_re,
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instr_din => rom_data,
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instr_addr => rom_addr,
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xmem_din => xmem_din,
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xmem_dout => xmem_dout,
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xmem_addr => xmem_addr,
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io_sel => io_sel
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);
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inst_irom: irom
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PORT MAP(
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clk => clk,
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ce => ce,
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addr => rom_addr,
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dout => rom_data
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);
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end rtl;
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