jens
2f7ab91e0d
git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
57 lines
1.2 KiB
Tcl
57 lines
1.2 KiB
Tcl
###########################################################################
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#
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# Generated by : Version 8.1 Build 163 10/28/2008 SJ Web Edition
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#
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# Project : eval_fixed_ja
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# Revision : eval_fixed_ja
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#
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# Date : Thu Dec 18 22:17:10 Westeuropäische Normalzeit 2008
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#
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###########################################################################
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# WARNING: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'
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# In SDC, create_generated_clock auto-generates clock latency
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#
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# ------------------------------------------
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#
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# Create generated clocks based on PLLs
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derive_pll_clocks -use_tan_name
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#
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# ------------------------------------------
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# ** Clock Latency
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# -------------
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# ** Clock Uncertainty
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# -----------------
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# ** Multicycles
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# -----------
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# ** Cuts
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# ----
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# ** Input/Output Delays
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# -------------------
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# ** Tpd requirements
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# ----------------
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# ** Setup/Hold Relationships
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# ------------------------
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# ** Tsu/Th requirements
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# -------------------
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# ** Tco/MinTco requirements
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# -----------------------
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# ---------------------------------------------
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