- separated bus-clock (sys_clk) and SDRAM-clocks - added async. FIFOs for clock domain separation Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@578 cc03376c-175c-47c8-b038-4cd826a8556b