152 lines
4.2 KiB
Smarty
152 lines
4.2 KiB
Smarty
-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: loadable ROM
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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library UNISIM;
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use UNISIM.VComponents.all;
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library work;
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use work.cpu_pkg.all;
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ENTITY xrom IS
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Port (
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clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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addr : in dmem_addr_t;
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dout : out dmem_data_t
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);
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END xrom;
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ARCHITECTURE loadable OF xrom IS
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-- JASM_ROM_INSERT_HERE
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signal jtag_ld_clk : STD_LOGIC;
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signal jtag_ld_we : STD_LOGIC;
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signal jtag_ld_addr : dmem_addr_t;
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signal jtag_ld_dout : dmem_data_t;
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signal jtag_ld_din : dmem_data_t;
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signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
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signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
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signal user_regi, user_rego : unsigned (15 downto 0);
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constant id : unsigned (15 downto 0) := X"BEEF";
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begin
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--------------------------------------------------------------------------
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-- Virtex-4: JTAG Loader
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--------------------------------------------------------------------------
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i00_BUFG : BUFG
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port map
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(
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O => bs_clk1,
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I => bs_clk0
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);
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i01_BUFG : BUFG
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port map
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(
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O => bs_update1,
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I => bs_update0
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);
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BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
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generic map
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(
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JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
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)
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port map
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(
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CAPTURE => bs_capture, -- CAPTURE output from TAP controller
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DRCK => bs_clk0, -- Data register output for USER functions
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RESET => bs_rst, -- Reset output from TAP controller
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SEL => bs_sel, -- USER active output
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SHIFT => bs_shift, -- SHIFT output from TAP controller
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TDI => bs_tdi, -- TDI output from TAP controller
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UPDATE => bs_update0, -- UPDATE output from TAP controller
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TDO => bs_tdo -- Data input for USER function
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);
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jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
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jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
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jtag_ld_clk <= bs_update1;
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jtag_ld_we <= bs_sel;
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sipo:
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process (bs_rst, bs_clk1, bs_tdi, bs_shift)
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begin
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if bs_rst = '1' then
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user_regi <= (others => '0');
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elsif rising_edge(bs_clk1) then
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if bs_shift = '1' then
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user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
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end if;
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end if;
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end process;
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piso:
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process (bs_rst, bs_clk1, bs_shift, user_rego)
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begin
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bs_tdo <= user_rego(0);
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if bs_rst = '1' then
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user_rego <= (others => '0');
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elsif rising_edge(bs_clk1) then
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if bs_shift = '1' then
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user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
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else
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user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
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-- user_rego <= id;
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end if;
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end if;
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end process;
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--------------------------------------------------------------------------
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-- ROM Read/Write
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--------------------------------------------------------------------------
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PROM_READ:
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process(clk, ce)
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begin
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if rising_edge(clk) and ce = '1' then
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dout <= xmem_rom(to_integer(addr));
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end if;
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end process;
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PROM_WRITE:
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process(jtag_ld_clk, jtag_ld_we)
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begin
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if rising_edge(jtag_ld_clk) then
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if jtag_ld_we = '1' then
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xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
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else
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jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
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end if;
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end if;
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end process;
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--------------------------------------------------------------------------
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end loadable;
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