jens
d61b3c2e0c
git-svn-id: http://moon:8086/svn/vhdl/trunk@1416 cc03376c-175c-47c8-b038-4cd826a8556b
434 lines
12 KiB
VHDL
434 lines
12 KiB
VHDL
-- Constant (K) Compact UART Transmitter
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--
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-- 9-Bit UART Transmitter
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--
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-- 9 data bits, no parity, 1 stop bit
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-- or
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-- 8 data bits, parity, 1 stop bit
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-- where the value of the parity bit must be computed externally and provided as data_in(8).
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--
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-- NOTE : This macro is intended to be attached to bbfifo_16x9 and operation requires the
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-- interaction of signals to and from that FIFO buffer to work correctly.
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--
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-- Version : 1.00 (derived from kcuart_tx version 1.10)
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-- Version Date : 10th February 2005
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--
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-- Ken Chapman
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-- Xilinx Ltd
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-- Benchmark House
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-- 203 Brooklands Road
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-- Weybridge
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-- Surrey KT13 ORH
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-- United Kingdom
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--
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-- chapman@xilinx.com
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--
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------------------------------------------------------------------------------------
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--
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-- NOTICE:
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--
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-- Copyright Xilinx, Inc. 2005. This code may be contain portions patented by other
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-- third parties. By providing this core as one possible implementation of a standard,
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-- Xilinx is making no representation that the provided implementation of this standard
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-- is free from any claims of infringement by any third party. Xilinx expressly
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-- disclaims any warranty with respect to the adequacy of the implementation, including
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-- but not limited to any warranty or representation that the implementation is free
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-- from claims of any third party. Futhermore, Xilinx is providing this core as a
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-- courtesy to you and suggests that you contact all third parties to obtain the
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-- necessary rights to use this implementation.
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--
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------------------------------------------------------------------------------------
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--
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-- Library declarations
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--
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-- The Unisim Library is used to define Xilinx primitives. It is also used during
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-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library unisim;
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use unisim.vcomponents.all;
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--
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------------------------------------------------------------------------------------
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--
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-- Main Entity for KCUART9_TX
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--
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entity kcuart9_tx is
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Port ( data_in : in std_logic_vector(8 downto 0);
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send_character : in std_logic;
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en_16_x_baud : in std_logic;
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serial_out : out std_logic;
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tx_complete : out std_logic;
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clk : in std_logic);
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end kcuart9_tx;
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--
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------------------------------------------------------------------------------------
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--
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-- Start of Main Architecture for KCUART9_TX
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--
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architecture low_level_definition of kcuart9_tx is
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--
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------------------------------------------------------------------------------------
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--
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------------------------------------------------------------------------------------
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--
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-- Signals used in KCUART9_TX
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--
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------------------------------------------------------------------------------------
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--
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signal data_01 : std_logic;
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signal data_23 : std_logic;
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signal data_45 : std_logic;
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signal data_67 : std_logic;
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signal data_0123 : std_logic;
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signal data_4567 : std_logic;
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signal data_01234567 : std_logic;
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signal data_01234567_reg : std_logic;
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signal data8_buf : std_logic;
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signal force_serial : std_logic;
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signal next_serial : std_logic;
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signal bit_count : std_logic_vector(2 downto 0);
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signal next_bit_count : std_logic_vector(2 downto 0);
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signal half_bit_count : std_logic_vector(2 downto 0);
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signal bit_count_cy : std_logic_vector(1 downto 0);
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signal baud_count : std_logic_vector(3 downto 0);
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signal next_baud_count : std_logic_vector(3 downto 0);
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signal half_baud_count : std_logic_vector(3 downto 0);
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signal baud_count_cy : std_logic_vector(3 downto 0);
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signal tx_bit_en : std_logic;
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signal decode7 : std_logic;
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signal sel_last_bit : std_logic;
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signal parity_bit : std_logic;
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signal next_transmit : std_logic;
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signal transmit : std_logic;
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signal next_tx_complete : std_logic;
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--
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--
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------------------------------------------------------------------------------------
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--
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-- Attributes to define LUT contents during implementation
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-- The information is repeated in the generic map for functional simulation--
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--
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------------------------------------------------------------------------------------
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--
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attribute INIT : string;
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attribute INIT of mux1_lut : label is "E4";
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attribute INIT of mux2_lut : label is "E4";
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attribute INIT of mux3_lut : label is "E4";
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attribute INIT of mux4_lut : label is "E4";
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attribute INIT of buf_data8 : label is "2";
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attribute INIT of force_lut : label is "E0FF";
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attribute INIT of count7_lut : label is "80";
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attribute INIT of transmit_lut : label is "32";
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attribute INIT of complete_lut : label is "8";
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--
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------------------------------------------------------------------------------------
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--
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-- Start of KCUART9_TX circuit description
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--
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------------------------------------------------------------------------------------
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--
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begin
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-- 8 to 1 multiplexer to convert parallel data to serial
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mux1_lut: LUT3
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--synthesis translate_off
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generic map (INIT => X"E4")
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--synthesis translate_on
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port map( I0 => bit_count(0),
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I1 => data_in(0),
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I2 => data_in(1),
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O => data_01 );
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mux2_lut: LUT3
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--synthesis translate_off
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generic map (INIT => X"E4")
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--synthesis translate_on
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port map( I0 => bit_count(0),
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I1 => data_in(2),
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I2 => data_in(3),
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O => data_23 );
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mux3_lut: LUT3
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--synthesis translate_off
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generic map (INIT => X"E4")
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--synthesis translate_on
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port map( I0 => bit_count(0),
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I1 => data_in(4),
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I2 => data_in(5),
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O => data_45 );
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mux4_lut: LUT3
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--synthesis translate_off
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generic map (INIT => X"E4")
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--synthesis translate_on
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port map( I0 => bit_count(0),
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I1 => data_in(6),
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I2 => data_in(7),
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O => data_67 );
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mux5_muxf5: MUXF5
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port map( I1 => data_23,
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I0 => data_01,
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S => bit_count(1),
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O => data_0123 );
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mux6_muxf5: MUXF5
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port map( I1 => data_67,
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I0 => data_45,
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S => bit_count(1),
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O => data_4567 );
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mux7_muxf6: MUXF6
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port map( I1 => data_4567,
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I0 => data_0123,
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S => bit_count(2),
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O => data_01234567 );
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pipeline_mux: FD
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port map ( D => data_01234567,
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Q => data_01234567_reg,
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C => clk);
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-- Serial output logic
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buf_data8: LUT1
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--synthesis translate_off
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generic map (INIT => X"2")
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--synthesis translate_on
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port map( I0 => data_in(8),
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O => data8_buf );
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force_lut: LUT4
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--synthesis translate_off
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generic map (INIT => X"E0FF")
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--synthesis translate_on
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port map( I0 => data_01234567_reg,
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I1 => parity_bit,
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I2 => transmit,
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I3 => send_character,
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O => force_serial );
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mux8_muxf5: MUXF5
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port map( I1 => data8_buf,
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I0 => force_serial,
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S => sel_last_bit,
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O => next_serial );
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-- Final output flip-flop initialised to start at '1'
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high_start: for i in 1 to 1 generate
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--
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attribute INIT : bit;
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attribute INIT of output_reg : label is '1';
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--
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begin
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output_reg: FDE
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--synthesis translate_off
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generic map (INIT => '1')
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--synthesis translate_on
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port map ( D => next_serial,
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Q => serial_out,
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CE => tx_bit_en,
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C => clk);
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end generate high_start;
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-- bit counter
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bit_count_loop: for i in 0 to 2 generate
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--
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attribute INIT : string;
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attribute INIT of bit_count_lut : label is "B";
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--
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begin
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bit_reg: FDE
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port map ( D => next_bit_count(i),
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Q => bit_count(i),
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CE => tx_bit_en,
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C => clk);
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bit_count_lut: LUT2
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--synthesis translate_off
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generic map (INIT => X"B")
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--synthesis translate_on
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port map( I0 => bit_count(i),
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I1 => transmit,
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O => half_bit_count(i));
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lsb_bit_count: if i=0 generate
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begin
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bit_count_xor: XORCY
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port map( LI => half_bit_count(i),
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CI => '1',
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O => next_bit_count(i));
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bit_count_muxcy: MUXCY
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port map( DI => '0',
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CI => '1',
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S => half_bit_count(i),
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O => bit_count_cy(i));
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end generate lsb_bit_count;
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upper_bit_count: if i>0 generate
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begin
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bit_count_xor: XORCY
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port map( LI => half_bit_count(i),
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CI => bit_count_cy(i-1),
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O => next_bit_count(i));
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middle_bit_count: if i=1 generate
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begin
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bit_count_muxcy: MUXCY
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port map( DI => '0',
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CI => bit_count_cy(i-1),
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S => half_bit_count(i),
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O => bit_count_cy(i));
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end generate middle_bit_count;
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end generate upper_bit_count;
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end generate bit_count_loop;
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-- baud counter
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baud_count_loop: for i in 0 to 3 generate
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--
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attribute INIT : string;
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attribute INIT of baud_count_lut : label is "2";
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--
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begin
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baud_reg: FDE
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port map ( D => next_baud_count(i),
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Q => baud_count(i),
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CE => en_16_x_baud,
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C => clk);
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baud_count_lut: LUT1
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--synthesis translate_off
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generic map (INIT => X"2")
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--synthesis translate_on
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port map( I0 => baud_count(i),
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O => half_baud_count(i));
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lsb_baud_count: if i=0 generate
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begin
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baud_count_xor: XORCY
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port map( LI => half_baud_count(i),
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CI => en_16_x_baud,
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O => next_baud_count(i));
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baud_count_muxcy: MUXCY
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port map( DI => '0',
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CI => en_16_x_baud,
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S => half_baud_count(i),
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O => baud_count_cy(i));
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end generate lsb_baud_count;
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upper_baud_count: if i>0 generate
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begin
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baud_count_xor: XORCY
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port map( LI => half_baud_count(i),
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CI => baud_count_cy(i-1),
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O => next_baud_count(i));
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baud_count_muxcy: MUXCY
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port map( DI => '0',
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CI => baud_count_cy(i-1),
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S => half_baud_count(i),
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O => baud_count_cy(i));
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end generate upper_baud_count;
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end generate baud_count_loop;
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bit_en_reg: FD
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port map ( D => baud_count_cy(3),
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Q => tx_bit_en,
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C => clk);
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-- state machine
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count7_lut: LUT3
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--synthesis translate_off
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generic map (INIT => X"80")
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--synthesis translate_on
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port map( I0 => bit_count(0),
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I1 => bit_count(1),
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I2 => bit_count(2),
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O => decode7 );
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sel_last_reg: FDE
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port map ( D => decode7,
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Q => sel_last_bit,
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CE => tx_bit_en,
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C => clk);
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parity_reg: FDE
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port map ( D => sel_last_bit,
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Q => parity_bit,
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CE => tx_bit_en,
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C => clk);
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transmit_lut: LUT3
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--synthesis translate_off
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generic map (INIT => X"32")
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--synthesis translate_on
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port map( I0 => send_character,
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I1 => parity_bit,
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I2 => transmit,
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O => next_transmit );
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transmit_reg: FDE
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port map ( D => next_transmit,
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Q => transmit,
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CE => tx_bit_en,
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C => clk);
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complete_lut: LUT2
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--synthesis translate_off
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generic map (INIT => X"8")
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--synthesis translate_on
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port map( I0 => parity_bit,
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I1 => tx_bit_en,
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O => next_tx_complete );
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complete_reg: FD
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port map ( D => next_tx_complete,
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Q => tx_complete,
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C => clk);
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end low_level_definition;
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------------------------------------------------------------------------------------
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--
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-- END OF FILE KCUART9_TX.VHD
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--
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------------------------------------------------------------------------------------
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