jens
d61b3c2e0c
git-svn-id: http://moon:8086/svn/vhdl/trunk@1416 cc03376c-175c-47c8-b038-4cd826a8556b
16 lines
500 B
Plaintext
16 lines
500 B
Plaintext
## NOTE: Do not edit this file.
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## Auto generated by Project Navigator for Post-PAR Simulation
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##
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vlib work
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## Compile Post-PAR Model
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vcom -explicit -93 "E:/work/VHDL/XilinxISE/Projects/PicoBlaze/netgen/par/kcpsm3_int_test_timesim.vhd"
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vcom -explicit -93 "test_bench.vhd"
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vsim -t 1ps -sdfmax /UUT=E:/work/VHDL/XilinxISE/Projects/PicoBlaze/netgen/par/kcpsm3_int_test_timesim.sdf -lib work testbench
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do {testbench.udo}
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view wave
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add wave *
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view structure
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view signals
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run 10us
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## End
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