jens cb8367c67a [DE0-Nano] ...

- reduce uart buffer to introduce more delay (work around for bus timeout)

git-svn-id: http://moon:8086/svn/vhdl/trunk@1361 cc03376c-175c-47c8-b038-4cd826a8556b

2016-12-21 21:14:07 +00:00

Common

- added

2015-10-24 16:12:48 +00:00

lib

[J-Uart]

2016-12-21 20:36:09 +00:00

projects

[DE0-Nano]

2016-12-21 21:14:07 +00:00

S

Description

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23 MiB

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VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%