jens
d61b3c2e0c
git-svn-id: http://moon:8086/svn/vhdl/trunk@1416 cc03376c-175c-47c8-b038-4cd826a8556b
78 lines
1.8 KiB
VHDL
78 lines
1.8 KiB
VHDL
-- Test Bench for kcpsm3_int_test.vhd
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--
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-- Ken Chapman - Xilinx Ltd - June 2003
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--
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY testbench IS
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END testbench;
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ARCHITECTURE behavior OF testbench IS
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-- Design to be tested
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COMPONENT kcpsm3_int_test
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Port ( counter : out std_logic_vector(7 downto 0);
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waveforms : out std_logic_vector(7 downto 0);
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interrupt_event : in std_logic;
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clk : in std_logic);
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END COMPONENT;
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-- signals to connect kcpsm3_int_test
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SIGNAL counter : std_logic_vector(7 downto 0);
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SIGNAL waveforms : std_logic_vector(7 downto 0);
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SIGNAL interrupt_event : std_logic := '0';
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SIGNAL clk : std_logic := '0';
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BEGIN
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-- Define the unit under test
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uut: kcpsm3_int_test
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port map ( counter => counter,
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waveforms => waveforms,
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interrupt_event => interrupt_event,
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clk => clk);
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-- Test Bench begins
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-- Nominal 50MHz clock which also defines number of cycles in simulation
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test_clock: process
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variable max_cycles : integer :=400;
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variable cycle_count : integer := 0;
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begin
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-- Define the clock cycles and the clock cycle counter
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while cycle_count < max_cycles loop
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clk <= '0';
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wait for 10 ns;
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clk <= '1';
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cycle_count := cycle_count + 1;
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wait for 10 ns;
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--Now define stimulus relative to a given clock cycle
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case cycle_count is
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when 30 => interrupt_event <= '1';
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when 67 => interrupt_event <= '1';
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when 183 => interrupt_event <= '1';
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when others => interrupt_event <= '0'; -- no interrupt
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end case;
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end loop;
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wait; -- end of simulation.
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end process;
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END;
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