vhdl/lib/uart/tb_uart.vhd

-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: cpu_embedded using cpu_core and rom
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity tb_uart is
end;

architecture behave of tb_uart is

	-- Number of user data words for simulation
	constant CLK_PERIOD		: time := 10 ns;
	constant BAUD_DIV		: natural := 2;

	-- Common
	signal rst				: std_logic := '1';  
	signal clk				: std_logic := '1';  
	signal en_16_x_baud		: std_logic := '1';  
	
	-- TX
	signal tx_we			: std_logic := '0';  
	signal ser_out			: std_logic;  
	signal tx_full			: std_logic;  
	signal tx_half_full		: std_logic;  
	signal tx_din			: unsigned(7 downto 0) := (others => '0');

	-- RX
	signal ser_in			: std_logic := '1';  
	signal rx_dout_vld		: std_logic;  
	signal rx_full			: std_logic;  
	signal rx_half_full		: std_logic;  
	signal rx_dout			: unsigned(7 downto 0);
	signal rx_re			: std_logic := '0';  
	
	-- Others
	signal baud_count		: unsigned(15 downto 0);
	signal baud_reg			: unsigned(15 downto 0) := to_unsigned(BAUD_DIV-1, baud_count'length);
	signal data_rx			: unsigned(7 downto 0);
	signal data_tx			: unsigned(7 downto 0);
	signal count_rx			: natural;

begin

	ser_in	<= ser_out;
	
inst_uart_tx : entity work.uart_tx
	PORT MAP
	(
		rst					=> rst,
		clk					=> clk,
		we					=> tx_we,
		din					=> tx_din,
		en_16_x_baud		=> en_16_x_baud,
		full				=> tx_full,
		half_full			=> tx_half_full,
		ser_out				=> ser_out
	);

inst_uart_rx : entity work.uart_rx
	PORT MAP
	(
		rst					=> rst,
		clk					=> clk,
		en_16_x_baud		=> en_16_x_baud,
		dout_vld			=> rx_dout_vld,
		dout				=> rx_dout,
		re					=> rx_re,
		full				=> rx_full,
		half_full			=> rx_half_full,
		ser_in				=> ser_in
	);

CLK_GEN: process
	begin
		wait for CLK_PERIOD/2;
		clk <= not clk;
	end process;

PROC_DATAREG_RX:
	process (clk)
	begin
		if rising_edge(clk) then
			if rst = '1' then
				count_rx <= 0;
			elsif rx_dout_vld = '1' and rx_re = '1' then
--				assert rx_dout = count_rx report "Data mismatch" severity failure;
				data_rx 	<= rx_dout;
				count_rx	<= count_rx + 1;
			end if;
		end if;
	end process;

PROC_RX_RE: process
	begin
		wait for 10 us;
		rx_re	<= rx_dout_vld;
	end process;

PROC_DATAREG_TX: process
	begin
		wait until rising_edge(clk) and tx_we = '1';
		data_tx <= tx_din;
	end process;

baud_timer:
process(clk)
begin
	if rising_edge(clk) then
		en_16_x_baud <= '0';
		if rst = '1' then
			baud_count <= (others => '0');
		elsif baud_count = baud_reg then
			baud_count <= (others => '0');
			en_16_x_baud <= '1';
		else
			baud_count <= baud_count + 1;
		end if;
	end if;
end process;

------------------------------------------------------------------------------------------

STIMULUS: process


	begin

		wait for 3*CLK_PERIOD;
		rst <= '0';
		wait for 3*CLK_PERIOD;
		wait until rising_edge(clk);
		
		for i in 0 to 255 loop
			wait until rising_edge(clk);
			tx_din <= to_unsigned(i, 8);
			tx_we <= '1';
			wait until rising_edge(clk) and tx_full = '0';
			tx_we <= '0';
		end loop;
		wait; 
	
	end process;
	
end architecture behave;