jens
010c1d2b65
git-svn-id: http://moon:8086/svn/vhdl/trunk@1426 cc03376c-175c-47c8-b038-4cd826a8556b
141 lines
2.9 KiB
VHDL
141 lines
2.9 KiB
VHDL
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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 17:08:52 04/08/2007
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-- Design Name: piso
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-- Module Name: tb_piso.vhd
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-- Project Name: piso_sipo
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: piso
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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ENTITY tb_piso_vhd IS
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GENERIC ( width : integer := 8);
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END tb_piso_vhd;
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ARCHITECTURE behavior OF tb_piso_vhd IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT piso
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GENERIC ( width : integer );
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PORT(
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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pdi : in UNSIGNED (width-1 downto 0);
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pvi : in STD_LOGIC;
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prdyo : out STD_LOGIC;
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sdo : out STD_LOGIC;
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sso : out STD_LOGIC;
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srdyi : in STD_LOGIC
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);
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END COMPONENT;
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CONSTANT CLK_PERIOD : time := 10 ns;
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--Inputs
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SIGNAL rst : std_logic := '1';
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SIGNAL clk : std_logic := '1';
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SIGNAL pvi : std_logic := '0';
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SIGNAL srdyi : std_logic := '0';
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SIGNAL pdi : UNSIGNED(width-1 downto 0) := (others=>'0');
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--Outputs
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SIGNAL prdyo : std_logic;
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SIGNAL sdo : std_logic;
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SIGNAL sso : std_logic;
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SIGNAL data : integer := 0;
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BEGIN
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clk_gen:
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PROCESS
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BEGIN
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wait for CLK_PERIOD/2;
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clk <= not clk;
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END PROCESS;
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-- Instantiate the Unit Under Test (UUT)
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uut: piso
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GENERIC MAP( width => width )
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PORT MAP(
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rst => rst,
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clk => clk,
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pdi => pdi,
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pvi => pvi,
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prdyo => prdyo,
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sdo => sdo,
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sso => sso,
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srdyi => srdyi
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);
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tb : PROCESS
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BEGIN
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-- Wait 100 ns for global reset to finish
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wait for 100 ns;
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rst <= '0';
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-- Place stimulus here
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wait; -- will wait forever
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END PROCESS;
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tb_srdy : process (rst, clk, sso)
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variable count : integer := 0;
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begin
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if rst = '1' then
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srdyi <= '0';
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count := 20;
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elsif rising_edge(clk) then
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if srdyi = '1' then
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if sso = '1' then
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srdyi <= '0';
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end if;
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else
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if count /= 0 then
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count := count - 1;
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else
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srdyi <= '1';
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count := 20;
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end if;
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end if;
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end if;
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end process;
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tb_sig : process (rst, clk, prdyo)
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begin
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if rst = '1' then
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data <= 0;
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elsif rising_edge(clk) then
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if prdyo = '1' then
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data <= data + 1;
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end if;
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end if;
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pdi <= to_unsigned(data, pdi'length);
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pvi <= prdyo;
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end process;
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END;
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