jens
2f7ab91e0d
git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
5 lines
200 B
Plaintext
5 lines
200 B
Plaintext
-- ProjNav VHDL simulation template: eval2clk_tb.udo
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-- You may edit this file after the line that starts with
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-- '-- START' to customize your simulation
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-- START user-defined simulation commands
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