jens
2edaa4d7cb
git-svn-id: http://moon:8086/svn/vhdl/trunk@1290 cc03376c-175c-47c8-b038-4cd826a8556b
346 lines
7.8 KiB
VHDL
346 lines
7.8 KiB
VHDL
---------------------------------------------------------------------------------
|
|
--COMMAND FORMAT --
|
|
-- --
|
|
-- write(column address(integer), bank(bit_vector), first data(integer), dqm(bit), cke(bit));--
|
|
-- read(column address(integer), bank(bit_vector), dqm(bit), cke(bit)); --
|
|
-- active(row address(integer), bank(bit_vector), data bus (integer), dqm(bit), cke(bit));--
|
|
-- precharge(bank(bit_vector), address (integer), data bus(integer), dqm(bit), cke(bit)); --
|
|
-- nop(data bus(integer), dqm(bit), cke(bit), cs(bit)); --
|
|
-- burst_term(data bus(integer), dqm(bit), cke(bit)); --
|
|
-- load_array('1'); --
|
|
-- load_mode_reg(register(integer), cke(bit)); --
|
|
-- next_cycle(clk); This is used after every command(incl. nop) to clock --
|
|
-- at the correct clock frequency entered in the clock --
|
|
-- period constant below --
|
|
-- unload_array(row_start(integer), row_end(integer), bank(bit_vector)) --
|
|
-- load_mode_reg(op_code(integer)) --
|
|
-- --
|
|
---------------------------------------------------------------------------------
|
|
|
|
LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
USE std.textio.all;
|
|
USE work.generate_vectors.all;
|
|
|
|
ENTITY vector_generate IS
|
|
END vector_generate;
|
|
|
|
ARCHITECTURE vector_generate OF vector_generate IS
|
|
|
|
SIGNAL stim_done : BOOLEAN := FALSE;
|
|
SIGNAL clk : BIT := '0';
|
|
CONSTANT clk_start : time := 15 ns;
|
|
CONSTANT clk_period : time := 10 ns;
|
|
CONSTANT Z : INTEGER := -100;
|
|
|
|
BEGIN
|
|
|
|
PROCESS
|
|
|
|
BEGIN
|
|
|
|
WAIT UNTIL clk = '1' AND clk'EVENT;
|
|
|
|
--------------------ENTER COMMANDS BELOW THIS LINE-----------------------------
|
|
--******************DO NOT USE -100 FOR A DQ VALUE*************************----
|
|
--*******************Z WILL PLACE HI-Z ON THE BUS**************************----
|
|
--*******USE next_cycle(clk) FOR ADVANCING TO NEXT CLOCK CYCLE*************----
|
|
|
|
nop(Z, '0', '1', '1'); --Always begin with one nop when using Micron's testbench
|
|
|
|
--next_cycle(clk);
|
|
--load_array('1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
precharge("00", 1024, Z, '0', '1');
|
|
|
|
FOR i IN 1 to 2 LOOP
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
END LOOP;
|
|
|
|
next_cycle(clk);
|
|
auto_refresh;
|
|
|
|
FOR i IN 1 TO 8 LOOP
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
END LOOP;
|
|
|
|
next_cycle(clk);
|
|
auto_refresh;
|
|
|
|
FOR i IN 1 TO 8 LOOP
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
END LOOP;
|
|
|
|
next_cycle(clk);
|
|
load_mode_reg(51, '1'); -- 19 / 35 / 51 -> lat=3,bl=8,mode=seq
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
-- Write Section
|
|
|
|
next_cycle(clk);
|
|
active(0, "00", Z, '0', '1'); -- Activate Bank 0
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk); -- Write Bank 0
|
|
write(10, "00", 0, '0', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(1, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
active(0, "01", 2, '0', '1'); -- Activate Bank 1
|
|
|
|
next_cycle(clk);
|
|
nop(3, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(4, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(5, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(6, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(7, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
write(20, "01", 8, '0', '1'); -- Write Bank 1
|
|
|
|
next_cycle(clk);
|
|
precharge("00", 0, 9, '0', '1'); -- Precharge Bank 0
|
|
|
|
next_cycle(clk);
|
|
active(0, "10", 10, '0', '1'); -- Activate Bank 2
|
|
|
|
next_cycle(clk);
|
|
nop(11, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(12, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(13, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(14, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(15, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
write(30, "10", 0, '0', '1'); -- Write Bank 2
|
|
|
|
next_cycle(clk);
|
|
precharge("01", 0, 1, '0', '1'); -- Precharge Bank 1
|
|
|
|
next_cycle(clk);
|
|
active(0, "11", 2, '0', '1'); -- Activate Bank 3
|
|
|
|
next_cycle(clk);
|
|
nop(3, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(4, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(5, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(6, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(7, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
write(40, "11", 8, '0', '1'); -- Write Bank 3
|
|
|
|
next_cycle(clk);
|
|
precharge("10", 0, 9, '0', '1'); -- Precharge Bank 2
|
|
|
|
next_cycle(clk);
|
|
active(0, "00", 10, '0', '1'); -- Activate Bank 0
|
|
|
|
next_cycle(clk);
|
|
nop(11, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(12, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(13, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(14, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(15, '0', '1', '1');
|
|
|
|
-- Read Section
|
|
|
|
next_cycle(clk);
|
|
read(10, "00", '0', '1'); -- Read Bank 0
|
|
|
|
next_cycle(clk);
|
|
precharge("11", 0, Z, '0', '1'); -- Precharge Bank 3
|
|
|
|
next_cycle(clk);
|
|
active(0, "01", Z, '0', '1'); -- Activate Bank 1
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
read(20, "01", '0', '1'); -- Read Bank 1
|
|
|
|
next_cycle(clk);
|
|
precharge("00", 0, Z, '0', '1'); -- Precharge Bank 0
|
|
|
|
next_cycle(clk);
|
|
active(0, "10", Z, '0', '1'); -- Activate Bank 2
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
read(30, "10", '0', '1'); -- Read Bank 2
|
|
|
|
next_cycle(clk);
|
|
precharge("01", 0, Z, '0', '1'); -- Precharge Bank 1
|
|
|
|
next_cycle(clk);
|
|
active(0, "11", Z, '0', '1'); -- Activate Bank 3
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
read(40, "11", '0', '1'); -- Read Bank 3
|
|
|
|
next_cycle(clk);
|
|
precharge("10", 0, Z, '0', '1'); -- Precharge Bank 2
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
precharge("11", 0, Z, '0', '1'); -- Precharge Bank 3
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
--next_cycle(clk);
|
|
--unload_array(0, 0, '0');
|
|
|
|
next_cycle(clk);
|
|
nop(Z, '0', '1', '1');
|
|
|
|
stim_done <= TRUE; --always include this line at the end of your stimulus
|
|
|
|
-------------------------------------------------------------------------------
|
|
--*************************************************************************----
|
|
END PROCESS;
|
|
|
|
|
|
clock:
|
|
PROCESS
|
|
VARIABLE done_time : time;
|
|
VARIABLE cycle_var : integer := 0;
|
|
BEGIN
|
|
cycle <= 0;
|
|
clk <= '0';
|
|
WAIT for clk_start;
|
|
WHILE not stim_done loop
|
|
clk <= '1';
|
|
cycle <= cycle_var;
|
|
WAIT for clk_period/2;
|
|
cycle_var := cycle_var + 1;
|
|
clk <= '0';
|
|
WAIT for clk_period/2;
|
|
END LOOP;
|
|
|
|
ASSERT (FALSE)
|
|
REPORT "Test Vectors Generated"
|
|
SEVERITY note;
|
|
|
|
WAIT;
|
|
END PROCESS;
|
|
|
|
|
|
END;
|