Files
vhdl/projects/hpi_reg/ise/hpi_reg_top.xst
T
jens 2f7ab91e0d - added
git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-21 12:04:37 +00:00

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set -tmpdir ./xst/projnav.tmp
set -xsthdpdir ./xst
run
-ifn hpi_reg_top.prj
-ifmt mixed
-ofn hpi_reg_top
-ofmt NGC
-p xc4vsx35-10-ff668
-top hpi_reg_top
-opt_mode Speed
-opt_level 1
-iuc NO
-lso hpi_reg_top.lso
-keep_hierarchy NO
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-mux_extract YES
-resource_sharing YES
-use_dsp48 auto
-iobuf YES
-max_fanout 500
-bufg 32
-bufr 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5