jens cd8a49ad18 - added blitter loop ...

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git-svn-id: http://moon:8086/svn/vhdl/trunk@677 cc03376c-175c-47c8-b038-4cd826a8556b

2009-11-22 22:37:20 +00:00

..

fonts

Initial import

2008-08-23 08:20:30 +00:00

char_gen.vhd

- turned all sys_clk-related async. resets to sys_clk synchronous resets

2009-11-07 15:00:51 +00:00

clkgen_virtex4.vhd

- added BUFG for clk_out

2009-11-04 10:39:14 +00:00

tb_vga_frontend64.vhd

- added blitter loop

2009-11-22 22:37:20 +00:00

tb_vga_frontend.vhd

- removed clkgen. VGA-clock generated in TB

2009-11-05 11:55:53 +00:00

vga_backend.vhd

- pulled out clkgen. vga_clk is now provided from higher level

2009-11-03 20:51:17 +00:00

vga_frontend64.vhd

- blitter FIFO is reseted on every new request

2009-11-22 22:35:55 +00:00

vga_frontend.vhd

- changed register rudimentary register layout (new offsets!)

2009-11-04 19:31:47 +00:00

vga_sync.vhd

Initial import

2008-08-23 08:20:30 +00:00

vga_timing.vhd

Initial import

2008-08-23 08:20:30 +00:00

vga_types.vhd

- set 'f_pxl_clk' of 'ts_vga_testbench' tp 40MHz

2009-11-22 13:52:27 +00:00