jens
2f7ab91e0d
git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
93 lines
1.7 KiB
VHDL
93 lines
1.7 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity main_top is
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Port ( res : in std_logic;
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clki : in std_logic;
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clko : out std_logic;
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di : in std_logic;
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do : out std_logic);
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end main_top;
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architecture Behavioral of main_top is
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type state_type is (idle, active, release);
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signal state, nextstate : state_type;
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signal clk : std_logic;
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shared variable test : std_logic;
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component BUFG
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port (I: in std_logic; O: out std_logic);
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end component;
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--**Insert the following after the 'begin' keyword**
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begin
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--U1: BUFG port map (I => clki, O => clk);
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clk <= clki;
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process (res, clk, di, state)
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begin
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if (res = '1') then
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clko <= '0';
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else
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clko <= '1';
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case state is
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when idle =>
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if (di = '1') then
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nextstate <= active;
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else
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nextstate <= idle;
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end if;
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when active =>
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if (di = '1') then
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nextstate <= active;
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else
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nextstate <= idle;
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end if;
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when release =>
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nextstate <= idle;
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end case;
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end if;
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end process;
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process (res, clk, state)
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begin
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if (res = '1') then
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do <= '0';
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else
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do <= '0';
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case state is
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when active =>
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do <= '1';
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when others =>
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end case;
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end if;
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end process;
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process (res, clk)
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begin
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if (res = '1') then
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state <= idle;
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elsif clk'event and clk = '1' then
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state <= nextstate;
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end if;
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end process;
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end Behavioral;
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