jens
b85b41e65d
git-svn-id: http://moon:8086/svn/vhdl/trunk@1037 cc03376c-175c-47c8-b038-4cd826a8556b
461 lines
12 KiB
VHDL
461 lines
12 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
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-- This file: Testbench for JCPU
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-- also writes 'opc.lst' for JASM-assembler
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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library work;
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use work.mips_types.all;
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use work.mips_instr.all;
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use work.async_types.all;
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use work.async_defs.all;
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ENTITY tb_mips_top IS
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END tb_mips_top;
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ARCHITECTURE behavior OF tb_mips_top IS
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constant SYS_FREQ : real := 100.0;
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constant CLK_PERIOD : time := 10 ns;
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constant SRAM_ADDR_WIDTH : integer := 17; -- bits
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constant FLASH_ADDR_WIDTH : integer := 17; -- bits
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signal debug : unsigned(1 downto 0);
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-- Master
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signal nmi : STD_LOGIC := '0';
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signal rst : STD_LOGIC := '1';
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signal clk : STD_LOGIC := '0';
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signal eb : STD_LOGIC := '1';
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signal ACK_I : STD_LOGIC := '0';
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signal SRDY_I : STD_LOGIC := '0';
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signal ADDR_O : unsigned(31 downto 0);
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signal DAT_I : unsigned(31 downto 0) := (others => '0');
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signal DAT_O : unsigned(31 downto 0);
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signal WE_O : STD_LOGIC;
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signal SEL_O : unsigned(3 downto 0);
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signal CYC_O : STD_LOGIC;
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signal STB_O : STD_LOGIC;
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signal MRDY_O : STD_LOGIC;
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signal INT : unsigned (5 downto 0) := (others => '0');
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-- Slaves
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signal CYC_I_rom : std_logic;
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signal ACK_O_rom : std_logic;
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signal SRDY_O_rom : std_logic;
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signal DAT_O_rom : unsigned(31 downto 0);
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signal CYC_I_flash : std_logic;
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signal ACK_O_flash : std_logic;
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signal SRDY_O_flash : std_logic;
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signal DAT_O_flash : unsigned(31 downto 0);
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signal CYC_I_sram : std_logic;
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signal ACK_O_sram : std_logic;
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signal SRDY_O_sram : std_logic;
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signal DAT_O_sram : unsigned(31 downto 0);
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signal CYC_I_gpio : std_logic;
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signal ACK_O_gpio : std_logic;
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signal SRDY_O_gpio : std_logic;
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signal DAT_O_gpio : unsigned(31 downto 0);
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signal CYC_I_uart : std_logic;
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signal ACK_O_uart : std_logic;
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signal SRDY_O_uart : std_logic;
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signal DAT_O_uart : unsigned(31 downto 0);
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signal flash_cs_n : std_logic;
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signal flash_we_n : std_logic;
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signal flash_oe_n : std_logic;
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signal flash_be_n : unsigned(3 downto 0);
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signal sram_cs_n : std_logic;
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signal sram_be_n : unsigned(3 downto 0);
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signal sram_wr_n : std_logic;
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signal sram_oe_n : std_logic;
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signal sram_a : unsigned(SRAM_ADDR_WIDTH-1 downto 0);
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signal sram_d : unsigned(31 downto 0);
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signal flash_a : unsigned(FLASH_ADDR_WIDTH-1 downto 0);
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signal flash_d : unsigned(31 downto 0);
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signal flash_page_mode_en : std_logic;
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signal gpi_0 : unsigned(31 downto 0);
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signal gpo_0 : unsigned(31 downto 0);
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signal int_timer : std_logic;
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signal int_uart : std_logic;
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signal rx : std_logic := '1';
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signal tx : std_logic;
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type mem_area_t is (mem_dead, mem_flash, mem_sram, mem_rom, mem_gpio, mem_uart);
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signal mem_area : mem_area_t;
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type word_array_t is array (natural range <>) of unsigned(31 downto 0);
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signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1);
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signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1);
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BEGIN
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------------------------------------------------------------------
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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clk <= not clk;
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end process;
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------------------------------------------------------------------
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-- Memory mux
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------------------------------------------------------------------
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mem_mux:
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process(ADDR_O)
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begin
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mem_area <= mem_dead;
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flash_page_mode_en <= '0';
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if ADDR_O(31 downto 28) = X"0" then
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mem_area <= mem_flash;
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flash_page_mode_en <= '1';
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elsif ADDR_O(31 downto 28) = X"A" then
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if ADDR_O(27 downto 26) = "00" then
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if ADDR_O(18 downto 16) = "000" then
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mem_area <= mem_gpio;
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elsif ADDR_O(18 downto 16) = "001" then
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mem_area <= mem_uart;
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end if;
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elsif ADDR_O(27 downto 26) = "01" then
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mem_area <= mem_flash;
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end if;
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elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
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mem_area <= mem_rom;
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elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
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mem_area <= mem_sram;
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end if;
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end process;
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signal_mux:
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process(mem_area, CYC_O)
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begin
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CYC_I_uart <= '0';
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CYC_I_gpio <= '0';
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CYC_I_flash <= '0';
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CYC_I_rom <= '0';
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CYC_I_sram <= '0';
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case mem_area is
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when mem_gpio =>
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CYC_I_gpio <= CYC_O;
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when mem_uart =>
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CYC_I_uart <= CYC_O;
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when mem_flash =>
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CYC_I_flash <= CYC_O;
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when mem_rom =>
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CYC_I_rom <= CYC_O;
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when mem_sram =>
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CYC_I_sram <= CYC_O;
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when others => null;
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end case;
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end process;
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SRDY_I <= SRDY_O_flash or SRDY_O_sram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio;
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ACK_I <= ACK_O_flash or ACK_O_sram or ACK_O_rom or ACK_O_uart or ACK_O_gpio;
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DAT_I <= DAT_O_sram when CYC_I_sram = '1' else
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DAT_O_rom when CYC_I_rom = '1' else
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DAT_O_flash when CYC_I_flash = '1' else
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DAT_O_uart when CYC_I_uart = '1' else
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DAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
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------------------------------------------------------------------
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uut: entity work.mips_top
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GENERIC MAP
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(
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icache_size => 1024, -- words
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dcache_size => 1024 -- words
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)
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PORT MAP
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(
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debug => debug,
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eb => eb,
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cpu_clk => clk,
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RST_I => rst,
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CLK_I => clk,
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ACK_I => ACK_I,
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SRDY_I => SRDY_I,
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ADDR_O => ADDR_O,
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DAT_I => DAT_I,
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DAT_O => DAT_O,
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WE_O => WE_O,
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SEL_O => SEL_O,
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CYC_O => CYC_O,
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STB_O => STB_O,
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MRDY_O => MRDY_O,
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INT => INT,
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nmi => nmi
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);
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INT(1) <= int_uart;
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INT(5) <= int_timer;
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inst_rom : entity work.rom_wb
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PORT MAP
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(
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CLK_I => clk,
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RST_I => rst,
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CYC_I => CYC_I_rom,
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STB_I => STB_O,
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WE_I => WE_O,
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ACK_O => ACK_O_rom,
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MRDY_I => MRDY_O,
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SRDY_O => SRDY_O_rom,
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ADDR_I => ADDR_O,
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DAT_O => DAT_O_rom
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);
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inst_gpio : entity work.gpio_wb
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PORT MAP
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(
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CLK_I => clk,
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RST_I => rst,
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CYC_I => CYC_I_gpio,
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STB_I => STB_O,
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SEL_I => SEL_O,
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WE_I => WE_O,
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ACK_O => ACK_O_gpio,
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SRDY_O => SRDY_O_gpio,
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MRDY_I => MRDY_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_O_gpio,
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INT_TIM_O => int_timer,
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sys_gpi_0 => gpi_0,
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sys_gpo_0 => gpo_0
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);
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inst_flash_port : entity work.async_port_wb
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GENERIC MAP
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(
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f_sysclk => SYS_FREQ,
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addr_width => FLASH_ADDR_WIDTH,
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data_width => 32,
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byte_sel_width => 4,
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async_timespec => ts_flash
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)
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PORT MAP
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(
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CLK_I => clk,
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RST_I => rst,
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CYC_I => CYC_I_flash,
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STB_I => STB_O,
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WE_I => WE_O,
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ACK_O => ACK_O_flash,
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SRDY_O => SRDY_O_flash,
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MRDY_I => MRDY_O,
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SEL_I => SEL_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_O_flash,
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page_mode_en => flash_page_mode_en,
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async_a => flash_a,
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async_d => flash_d,
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async_cs => flash_cs_n,
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async_wr => flash_we_n,
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async_rd => flash_oe_n,
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async_be => flash_be_n,
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async_rst => open
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);
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inst_sram_port : entity work.async_port_wb
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GENERIC MAP
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(
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f_sysclk => SYS_FREQ,
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addr_width => SRAM_ADDR_WIDTH,
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data_width => 32,
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byte_sel_width => 4,
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async_timespec => ts_sram
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)
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PORT MAP
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(
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CLK_I => clk,
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RST_I => rst,
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CYC_I => CYC_I_sram,
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STB_I => STB_O,
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WE_I => WE_O,
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ACK_O => ACK_O_sram,
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SRDY_O => SRDY_O_sram,
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MRDY_I => MRDY_O,
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SEL_I => SEL_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_O_sram,
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page_mode_en => '0',
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async_a => sram_a,
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async_d => sram_d,
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async_cs => sram_cs_n,
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async_wr => sram_wr_n,
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async_rd => sram_oe_n,
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async_be => sram_be_n,
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async_rst => open
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);
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inst_uart : entity work.uart_wb
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GENERIC MAP
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(
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simulate_tx => true
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)
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PORT MAP
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(
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CLK_I => clk,
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RST_I => rst,
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CYC_I => CYC_I_uart,
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STB_I => STB_O,
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SEL_I => SEL_O,
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WE_I => WE_O,
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ACK_O => ACK_O_uart,
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SRDY_O => SRDY_O_uart,
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MRDY_I => MRDY_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_O_uart,
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INT_O => int_uart,
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ser_rx => rx,
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ser_tx => tx
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);
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------------------------------------------------------------------
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SRAM_READ:
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process(sram_a, sram_cs_n, sram_oe_n, sram_be_n)
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begin
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sram_d <= (others => 'Z') after 10 ns;
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if sram_oe_n = '0' then
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if sram_cs_n = '0' then
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if sram_be_n(0) = '0' then
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sram_d(7 downto 0) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) after 10 ns;
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end if;
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if sram_be_n(1) = '0' then
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sram_d(15 downto 8) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) after 10 ns;
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end if;
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if sram_be_n(2) = '0' then
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sram_d(23 downto 16) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) after 10 ns;
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end if;
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if sram_be_n(3) = '0' then
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sram_d(31 downto 24) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) after 10 ns;
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end if;
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end if;
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end if;
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end process;
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SRAM_WRITE:
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process(sram_wr_n)
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begin
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if rising_edge(sram_wr_n) then
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if sram_cs_n = '0' then
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if sram_be_n(0) = '0' then
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sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0);
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end if;
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if sram_be_n(1) = '0' then
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sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8);
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end if;
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if sram_be_n(2) = '0' then
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sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16);
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end if;
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if sram_be_n(3) = '0' then
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sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24);
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end if;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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FLASH_READ:
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process(rst, flash_cs_n, flash_oe_n, flash_a)
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type file_t is file of integer;
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-- file load_flash : file_t open read_mode is "ucb.elf.flash.bin";
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file load_flash : file_t open read_mode is "test_timer.elf.flash.bin";
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-- file load_flash : file_t open read_mode is "test_dcache.flash.bin";
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variable instr : integer;
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variable index : natural;
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variable temp : signed(31 downto 0);
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constant tpd : time := 25 ns;
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begin
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if rst = '1' then
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index := 0;
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while not endfile(load_flash) loop
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read(load_flash, instr);
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temp := to_signed(instr, word_t'length);
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flash_data(index) <= unsigned(temp);
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index := index + 1;
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end loop;
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else
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flash_d <= (others => 'Z') after tpd;
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index := to_integer(flash_a(FLASH_ADDR_WIDTH-1 downto 2));
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if flash_oe_n = '0' then
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if flash_cs_n = '0' then
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if flash_be_n(0) = '0' then
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flash_d(7 downto 0) <= flash_data(index)(7 downto 0) after tpd;
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end if;
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if flash_be_n(1) = '0' then
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flash_d(15 downto 8) <= flash_data(index)(15 downto 8) after tpd;
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end if;
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if flash_be_n(2) = '0' then
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flash_d(23 downto 16) <= flash_data(index)(23 downto 16) after tpd;
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end if;
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if flash_be_n(3) = '0' then
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flash_d(31 downto 24) <= flash_data(index)(31 downto 24) after tpd;
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end if;
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end if;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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STIMULUS: process
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begin
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gpi_0 <= X"00000000";
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wait for 3*CLK_PERIOD;
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wait until rising_edge(clk);
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rst <= '0';
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wait for 778254*CLK_PERIOD;
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wait until rising_edge(clk);
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nmi <= '0';
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wait for 3000*CLK_PERIOD;
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wait until rising_edge(clk);
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nmi <= '0';
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wait;
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end process;
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END;
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