jens b2c5bcb279 - minor changes to frontend ...

- increased POWER_UP wait
- added reset delay

git-svn-id: http://moon:8086/svn/vhdl/trunk@1259 cc03376c-175c-47c8-b038-4cd826a8556b

2015-05-29 19:18:52 +00:00

Common

- added altera_mf

2015-05-29 13:15:53 +00:00

lib

- minor changes to frontend

2015-05-29 19:18:52 +00:00

projects/mips_sys

- update

2015-05-28 08:44:58 +00:00

S

Description

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23 MiB

Languages

VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%