jens
2f7ab91e0d
git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
87 lines
2.1 KiB
VHDL
87 lines
2.1 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity main_top is
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Port ( clk : in std_logic;
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resn : in std_logic;
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a : in std_logic_vector(31 downto 0);
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d : inout std_logic_vector(31 downto 0);
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wen : in std_logic;
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csn : in std_logic);
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end main_top;
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architecture Behavioral of main_top is
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type t_reg is array (31 downto 0) of std_logic ;
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signal reg_a, reg_b, reg_c : t_reg;
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signal cs_a, cs_b, cs_c, CI, CO : std_logic;
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signal dmuxo : std_logic_vector(31 downto 0);
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signal mux_ctrl : std_logic_vector (3 downto 0);
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signal AA,BB,S31: std_logic_vector(32-1 downto 0);
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signal sum : std_logic_vector(32 downto 0);
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signal zeros: std_logic_vector(32-1 downto 0) := (others => '0');
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begin
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mux_ctrl <= a(7 downto 4);
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dmuxo <= std_logic_vector(reg_a) when (mux_ctrl = X"0") else
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std_logic_vector(reg_b) when (mux_ctrl = X"1") else
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std_logic_vector(reg_c) when (mux_ctrl = X"2") else
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X"12345678";
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cs_a <= '1' when (mux_ctrl = X"0" and csn = '0') else '0';
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cs_b <= '1' when (mux_ctrl = X"1" and csn = '0') else '0';
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cs_c <= '1' when (mux_ctrl = X"2" and csn = '0') else '0';
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CI <= wen;
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AA <= dmuxo when (wen = '1' and csn = '0') else (31 downto 0 => 'Z');
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BB <=a;
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d <= S31;
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write_reg_a: process (clk, wen, cs_a, d)
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begin
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if clk'event and clk = '0' then
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if (wen = '0' and cs_a = '1') then
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reg_a <= t_reg(d);
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end if;
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end if;
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end process;
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write_reg_b: process (clk, wen, cs_b, d)
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begin
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if clk'event and clk = '0' then
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if (wen = '0' and cs_b = '1') then
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reg_b <= t_reg(d);
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end if;
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end if;
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end process;
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write_reg_c: process (clk, wen, cs_c, d)
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begin
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if clk'event and clk = '0' then
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if (wen = '0' and cs_c = '1') then
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reg_c <= t_reg(d);
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end if;
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end if;
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end process;
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process (CI, AA, BB, sum)
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begin
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sum <= ('0' & AA) + ('0' & BB) + (zeros & CI);
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S31 <= sum(32-1 downto 0);
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CO <= sum(32);
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end process;
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end Behavioral;
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