jens
2f7ab91e0d
git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
54 lines
1.2 KiB
VHDL
54 lines
1.2 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 13:19:14 10/08/05
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-- Design Name:
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-- Module Name: d_ff - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity d_ff is
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Generic (
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tpd : time := 1 ns
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);
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Port ( rst : in std_logic;
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clk : in std_logic;
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din : in std_logic;
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dout : out std_logic);
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end d_ff;
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architecture Behavioral of d_ff is
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begin
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d_ff_proc : process(rst, clk, din)
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begin
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if (rst = '1') then
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dout <= '0' after tpd;
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elsif rising_edge(clk) then
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dout <= din after tpd;
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end if;
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end process;
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end Behavioral;
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