jens
db9e21023c
- added simulation entities git-svn-id: http://moon:8086/svn/vhdl/trunk@1079 cc03376c-175c-47c8-b038-4cd826a8556b
56 lines
1.6 KiB
VHDL
56 lines
1.6 KiB
VHDL
LIBRARY IEEE;
|
|
USE IEEE.STD_LOGIC_1164.ALL;
|
|
USE IEEE.NUMERIC_STD.ALL;
|
|
--
|
|
------------------------------------------------------------------------------------
|
|
--
|
|
-- Main Entity for UART_RX
|
|
--
|
|
entity uart_rx is
|
|
Port ( serial_in : in std_logic;
|
|
data_out : out std_logic_vector(7 downto 0);
|
|
read_buffer : in std_logic;
|
|
reset_buffer : in std_logic;
|
|
en_16_x_baud : in std_logic;
|
|
buffer_data_present : out std_logic;
|
|
buffer_full : out std_logic;
|
|
buffer_half_full : out std_logic;
|
|
clk : in std_logic);
|
|
end uart_rx;
|
|
--
|
|
------------------------------------------------------------------------------------
|
|
--
|
|
-- Start of Main Architecture for UART_RX
|
|
--
|
|
architecture behavior of uart_rx is
|
|
--
|
|
------------------------------------------------------------------------------------
|
|
--
|
|
-- Signals used in UART_RX
|
|
--
|
|
------------------------------------------------------------------------------------
|
|
--
|
|
--
|
|
------------------------------------------------------------------------------------
|
|
--
|
|
-- Start of UART_RX circuit description
|
|
--
|
|
------------------------------------------------------------------------------------
|
|
--
|
|
begin
|
|
|
|
data_out <= X"00";
|
|
buffer_data_present <= '0';
|
|
buffer_full <= '0';
|
|
buffer_half_full <= '0';
|
|
|
|
end behavior;
|
|
|
|
------------------------------------------------------------------------------------
|
|
--
|
|
-- END OF FILE UART_RX.VHD
|
|
--
|
|
------------------------------------------------------------------------------------
|
|
|
|
|