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vhdl/lib/CPUs/MIPS/syn/ise101/project/mips_top.xcf
T
jens 8e7477b83b - try to add clock buffer constraint
git-svn-id: http://moon:8086/svn/vhdl/trunk@1619 cc03376c-175c-47c8-b038-4cd826a8556b
2021-04-02 12:42:01 +00:00

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# CPU clock nets
NET "cpu_clk" TNM_NET = "cpu_clk";
TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk" 9.9 ns HIGH 50 %;
# Bus clock nets
NET "CLK_I" TNM_NET = "bus_clk";
TIMESPEC "TS_bus_clk" = PERIOD "bus_clk" 9.9 ns HIGH 50 %;
BEGIN MODEL biu
INST inst_bin_fifo ram_style = distributed;
INST inst_bout_fifo ram_style = distributed;
INST inst_write_fifo ram_style = distributed;
END;
BEGIN MODEL mips_top
NET cpu_clk clock_buffer = true;
NET cpu_clk buffer_type = bufg;
NET CLK_I clock_buffer = true;
NET CLK_I buffer_type = bufg;
END;