jens
8b49c6197c
- added assertion check for zero r/w-pulses Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@535 cc03376c-175c-47c8-b038-4cd826a8556b
302 lines
7.0 KiB
VHDL
302 lines
7.0 KiB
VHDL
-----------------------------------------------------------------------
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-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.6 2009-10-27 21:25:36 Jens Exp $
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.async_types.all;
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------------------------------------------------------------------
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entity async_port_wb is
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Generic
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(
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addr_width : natural := 32;
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data_width : natural := 32;
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byte_sel_width : natural := 4;
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async_timespec : async_timespec_t
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);
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Port
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(
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CLK_I : in STD_LOGIC;
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RST_I : in STD_LOGIC;
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CYC_I : in STD_LOGIC;
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STB_I : in STD_LOGIC;
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WE_I : in STD_LOGIC;
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ACK_O : out STD_LOGIC;
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SRDY_O : out STD_LOGIC;
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MRDY_I : in STD_LOGIC;
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SEL_I : in unsigned(3 downto 0);
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ADDR_I : in unsigned(31 downto 0);
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DAT_I : in unsigned(31 downto 0);
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DAT_O : out unsigned(31 downto 0);
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async_a : out unsigned(addr_width-1 downto 0);
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async_d : inout unsigned(data_width-1 downto 0);
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async_cs : out std_logic;
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async_wr : out std_logic;
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async_rd : out std_logic;
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async_be : out unsigned(byte_sel_width-1 downto 0);
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async_rst : out std_logic
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);
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end async_port_wb;
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architecture Behavioral of async_port_wb is
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type async_t is record
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cs : std_logic;
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wr : std_logic;
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rd : std_logic;
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rst : std_logic;
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drive_d : std_logic;
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end record;
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type async_state_t is (start, reset, idle, leadin, pulse, leadout, release);
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signal s, sn : async_state_t;
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signal as : async_t;
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signal ack : std_logic;
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signal cc_rst : std_logic;
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signal cycle_cnt : natural range 0 to 15;
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signal cycle_reload : natural range 0 to 15;
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signal rdy : std_logic;
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signal rdyo : std_logic;
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signal en : std_logic;
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signal data_reg : unsigned(data_width-1 downto 0);
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signal byte_en : unsigned(byte_sel_width-1 downto 0);
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signal write : std_logic;
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------------------------------------------------------------------
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begin
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ASSERT async_timespec.ncyc_pulse_rd > 0 report "Read pulse length must be greater than zero!" severity failure;
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ASSERT async_timespec.ncyc_pulse_wr > 0 report "Write pulse length must be greater than zero!" severity failure;
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SRDY_O <= CYC_I and rdyo;
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en <= CYC_I and STB_I;
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proc_cycle_counter:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if cc_rst = '1' then
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cycle_cnt <= cycle_reload;
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elsif cycle_cnt /= 0 then
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cycle_cnt <= cycle_cnt - 1;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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proc_state_next:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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s <= start;
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else
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s <= sn;
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end if;
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end if;
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end process;
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proc_state:
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process(s, cycle_cnt, en, write, WE_I)
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begin
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cycle_reload <= async_timespec.ncyc_pulse_rst;
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cc_rst <= '0';
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as.rst <= '0';
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as.cs <= '0';
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as.wr <= '0';
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as.rd <= '0';
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as.drive_d <= '0';
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ack <= '0';
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rdy <= '0';
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sn <= s;
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case s is
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when start =>
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cc_rst <= '1';
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sn <= reset;
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when reset =>
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as.rst <= '1';
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if cycle_cnt = 0 then
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sn <= idle;
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end if;
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when idle =>
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rdy <= '1';
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if en = '1' then
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as.cs <= '1';
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cc_rst <= '1';
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if async_timespec.ncyc_leadin = 0 then
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sn <= pulse;
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if WE_I = '1' then
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cycle_reload <= async_timespec.ncyc_pulse_wr-1;
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as.wr <= '1';
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as.drive_d <= '1';
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else
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cycle_reload <= async_timespec.ncyc_pulse_rd-1;
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as.rd <= '1';
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end if;
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else
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cycle_reload <= async_timespec.ncyc_leadin-1;
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sn <= leadin;
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end if;
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end if;
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when leadin =>
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as.cs <= '1';
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if cycle_cnt = 0 then
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cc_rst <= '1';
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sn <= pulse;
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if write = '1' then
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cycle_reload <= async_timespec.ncyc_pulse_wr-1;
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as.wr <= '1';
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as.drive_d <= '1';
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else
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cycle_reload <= async_timespec.ncyc_pulse_rd-1;
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as.rd <= '1';
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end if;
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end if;
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when pulse =>
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as.cs <= '1';
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as.rd <= not write;
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as.drive_d <= write;
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as.wr <= write;
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if cycle_cnt = 0 then
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as.wr <= '0';
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as.rd <= '0';
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cc_rst <= '1';
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ack <= not write;
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if async_timespec.ncyc_leadout = 0 then
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as.cs <= '0';
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if async_timespec.ncyc_release = 0 then
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sn <= idle;
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else
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cycle_reload <= async_timespec.ncyc_release-1;
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sn <= release;
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end if;
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else
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cycle_reload <= async_timespec.ncyc_leadout-1;
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sn <= leadout;
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end if;
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end if;
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when leadout =>
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as.cs <= '1';
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if cycle_cnt = 0 then
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cc_rst <= '1';
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as.cs <= '0';
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if async_timespec.ncyc_release = 0 then
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sn <= idle;
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else
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cycle_reload <= async_timespec.ncyc_release-1;
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sn <= release;
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end if;
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end if;
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when release =>
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if cycle_cnt = 0 then
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sn <= idle;
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end if;
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when others =>
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sn <= idle;
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end case;
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end process;
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------------------------------------------------------------------
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output_ctrl:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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async_cs <= (not async_timespec.pol_cs) xor as.cs;
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async_be <= (byte_sel_width-1 downto 0 => not async_timespec.pol_be) xor ((byte_sel_width-1 downto 0 => as.cs) and byte_en);
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async_wr <= (not async_timespec.pol_we) xor as.wr;
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async_rd <= (not async_timespec.pol_oe) xor as.rd;
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async_rst <= (not async_timespec.pol_rst) xor as.rst;
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end if;
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end process;
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------------------------------------------------------------------
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din_register:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if as.rd = '1' then
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DAT_O(data_width-1 downto 0) <= async_d;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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output_addr:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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async_a <= (others => '0');
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byte_en <= (others => '0');
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elsif en = '1' and rdy = '1' then
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async_a <= ADDR_I(addr_width-1 downto 0);
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byte_en <= SEL_I(byte_sel_width-1 downto 0);
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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data_register:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if en = '1' and rdy = '1' then
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data_reg <= DAT_I(data_width-1 downto 0);
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write <= WE_I;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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output_SRDY:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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rdyo <= '1';
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elsif en = '1' then
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rdyo <= rdy and not rdyo;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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output_ACK:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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ACK_O <= '0';
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else
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ACK_O <= ack;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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output_data:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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async_d <= (others => 'Z');
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if as.drive_d = '1' then
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async_d <= data_reg;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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end Behavioral;
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