jens
5309734167
git-svn-id: http://moon:8086/svn/vhdl/trunk@1422 cc03376c-175c-47c8-b038-4cd826a8556b
66 lines
1.5 KiB
VHDL
66 lines
1.5 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 19:20:09 10/22/05
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-- Design Name:
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-- Module Name: timeout_counter - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity timeout_counter is
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Generic (N : integer := 8);
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Port ( rst : in std_logic;
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clk : in std_logic;
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ce : in std_logic;
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load : in integer range 0 to N-1;
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load_en : in std_logic;
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rdy : out std_logic);
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end timeout_counter;
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architecture Behavioral of timeout_counter is
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signal count : integer range 0 to N-1;
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begin
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process (rst, clk, ce, load, load_en)
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begin
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if rst='1' then
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count <= load;
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rdy <= '0';
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elsif clk='1' and clk'event then
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rdy <= '0';
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if load_en ='1' then
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count <= load;
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else
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if (count /= 0) then
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if ce ='1' then
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count <= count - 1;
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end if;
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else
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rdy <= '1';
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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