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-- Company: 
-- Engineer:
--
-- Create Date:    19:20:09 10/22/05
-- Design Name:    
-- Module Name:    timeout_counter - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity timeout_counter is
	 Generic (N : integer := 8);
    Port ( rst : in std_logic;
           clk : in std_logic;
           ce : in std_logic;
           load : in integer range 0 to N-1;
           load_en : in std_logic;
           rdy : out std_logic);
end timeout_counter;

architecture Behavioral of timeout_counter is
signal count : integer range 0 to N-1;
begin

process (rst, clk, ce, load, load_en) 
begin
   if rst='1' then 
      count <= load;
		rdy <= '0'; 
   elsif clk='1' and clk'event then
		rdy <= '0'; 
      if load_en ='1' then
         count <= load;
      else
			if (count /= 0) then
		      if ce ='1' then
	           	count <= count - 1;
				end if;
			else
				rdy <= '1';
			end if;		
      end if;
   end if;
end process;

end Behavioral;