81 lines
1.3 KiB
VHDL
81 lines
1.3 KiB
VHDL
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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ENTITY ram_wb IS
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Port
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(
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CLK_I : in STD_LOGIC;
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RST_I : in STD_LOGIC;
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CYC_I : in STD_LOGIC;
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STB_I : in STD_LOGIC;
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SEL_I : in unsigned(3 downto 0);
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WE_I : in STD_LOGIC;
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ACK_O : out STD_LOGIC;
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SRDY_O : out STD_LOGIC;
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MRDY_I : in STD_LOGIC;
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ADDR_I : in unsigned(31 downto 0);
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DAT_I : in unsigned(31 downto 0);
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DAT_O : out unsigned(31 downto 0)
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);
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END ram_wb;
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ARCHITECTURE behavior OF ram_wb IS
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COMPONENT ram
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GENERIC
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(
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word_addr_width : integer
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);
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PORT
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(
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clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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we : in unsigned(3 downto 0);
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addr : in unsigned(31 downto 0);
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din : in unsigned(31 downto 0);
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dout : out unsigned(31 downto 0)
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);
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END COMPONENT;
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signal data_en : std_logic;
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signal we : unsigned(3 downto 0);
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begin
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we <= SEL_I and (3 downto 0 => WE_I);
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data_en <= CYC_I and STB_I and MRDY_I;
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SRDY_O <= CYC_I;
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data_valid_register:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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ACK_O <= '0';
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else
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ACK_O <= data_en and not WE_I;
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end if;
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end if;
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end process;
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inst_ram : ram
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GENERIC MAP
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(
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word_addr_width => 6
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)
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PORT MAP
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(
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clk => CLK_I,
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ce => data_en,
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we => we,
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addr => ADDR_I,
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din => DAT_I,
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dout => DAT_O
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);
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end behavior;
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