jens 7668dd7814 - fixed delta delay. clk0 is generated and evaluated ddr_phy_virtex4 in simulation step n. ...

Entities using clk0_out are evaluated in simulation step n+1, causing data sampling during data change.

git-svn-id: http://moon:8086/svn/vhdl/trunk@1160 cc03376c-175c-47c8-b038-4cd826a8556b

2015-05-23 07:38:25 +00:00

..

doc

- Minor changes

2009-11-04 00:20:00 +00:00

sim

- ignore

2015-05-23 05:24:45 +00:00

src

- fixed delta delay. clk0 is generated and evaluated ddr_phy_virtex4 in simulation step n.

2015-05-23 07:38:25 +00:00

todo.txt

update

2009-11-15 10:21:45 +00:00