jens 7668dd7814 - fixed delta delay. clk0 is generated and evaluated ddr_phy_virtex4 in simulation step n. ...

Entities using clk0_out are evaluated in simulation step n+1, causing data sampling during data change.

git-svn-id: http://moon:8086/svn/vhdl/trunk@1160 cc03376c-175c-47c8-b038-4cd826a8556b

2015-05-23 07:38:25 +00:00

Common

- added unisim sources

2015-05-20 05:48:08 +00:00

lib

- fixed delta delay. clk0 is generated and evaluated ddr_phy_virtex4 in simulation step n.

2015-05-23 07:38:25 +00:00

projects/mips_sys

- use old bootloader and run dhrystone

2015-05-22 22:10:13 +00:00

S

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23 MiB

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VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%