jens 697150b619 - reduced verbosity ...

git-svn-id: http://moon:8086/svn/vhdl/trunk@1395 cc03376c-175c-47c8-b038-4cd826a8556b

2021-03-19 13:35:58 +00:00

Common

- prepared synth target

2021-03-19 11:42:32 +00:00

lib

- reduced verbosity

2021-03-19 13:35:58 +00:00

projects

- automatically build netlist in /lib/MIPS/syn

2021-03-18 16:34:29 +00:00

S

Description

No description provided

23 MiB

Languages

VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%