jens
3bb2a235f5
git-svn-id: http://moon:8086/svn/vhdl/trunk@1512 cc03376c-175c-47c8-b038-4cd826a8556b
81 lines
2.3 KiB
VHDL
81 lines
2.3 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: Dual-ported register file with asynchrous read
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-- Copyright (C) 2007 J. Ahrensfeld
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-- This library is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- This library is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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-- For questions and ideas, please contact the author at jens@jayfield.org
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-----------------------------------------------------------------------
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-- $Header: D:\usr\cvsroot/VHDL/lib/misc/dpram_1w2r1c_xil.vhd,v 1.1 2013/02/07 14:15:38 jens Exp $
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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entity dpram_1w2r1c is
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Generic
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(
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addr_width : integer := 3;
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data_width : integer := 8
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);
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Port
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(
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clk : in STD_LOGIC;
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en_a : in STD_LOGIC;
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en_b : in STD_LOGIC;
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we_a : in STD_LOGIC;
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addr_a : in unsigned (addr_width-1 downto 0);
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addr_b : in unsigned (addr_width-1 downto 0);
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din_a : in unsigned (data_width-1 downto 0);
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dout_a : out unsigned (data_width-1 downto 0);
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dout_b : out unsigned (data_width-1 downto 0)
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);
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end dpram_1w2r1c;
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architecture Behavioral of dpram_1w2r1c is
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begin
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inst_dpram: entity work.dpram_2w2r2c
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GENERIC MAP
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(
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addr_width => addr_width,
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data_width => data_width
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)
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PORT MAP
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(
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clk_a => clk,
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clk_b => clk,
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en_a => en_a,
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en_b => en_b,
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we_a => we_a,
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we_b => '0',
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addr_a => addr_a,
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addr_b => addr_b,
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din_a => din_a,
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din_b => din_a,
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dout_a => dout_a,
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dout_b => dout_b
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);
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end Behavioral;
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