Files
vhdl/lib/JBUS/memory/ghdl/tb_rom_wb.make
T
jens 06feba8f63 - refactored
git-svn-id: http://moon:8086/svn/vhdl/trunk@1541 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-28 10:27:33 +00:00

17 lines
301 B
Makefile

include $(VHDL_HOME)/make/defs.mk
MOD_PATH := $(LIB_PATH)/JBUS/memory
SRCS += $(MOD_PATH)/src/rom_sim.vhd
SRCS += $(MOD_PATH)/src/rom_wb.vhd
SRCS += $(MOD_PATH)/src/tb_rom_wb.vhd
# Compile
TARGET := tb_rom_wb
ENTITY := tb_rom_wb
WITH_VCD := y
RUN_TIME := 1500ns
include $(VHDL_HOME)/make/ghdl.mk