jens
1abe64b3b4
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@882 cc03376c-175c-47c8-b038-4cd826a8556b
107 lines
2.6 KiB
VHDL
107 lines
2.6 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: testbench for system test using Xilinx ML-402
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-- Copyright (C) 2007 J. Ahrensfeld
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-- This library is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- This library is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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-- For questions and ideas, please contact the author at jens@jayfield.org
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-----------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY tb_crc32 IS
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END tb_crc32;
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ARCHITECTURE behavior OF tb_crc32 IS
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constant CLK_PERIOD : time := 10 ns;
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signal CLK : std_logic := '1';
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signal RST : std_logic := '1';
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signal din_vld : std_logic := '0';
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signal din : unsigned(7 downto 0) := (others => '-');
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signal crc32 : unsigned(31 downto 0);
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signal crc32_vld : std_logic;
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type byte_array_t is array (0 to 61) of unsigned(7 downto 0);
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signal test_data : byte_array_t :=
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(
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X"00", X"0A", X"E6", X"F0", X"05", X"A3", X"00", X"12",
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X"34", X"56", X"78", X"90", X"08", X"00", X"45", X"00",
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X"00", X"30", X"B3", X"FE", X"00", X"00", X"80", X"11",
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X"72", X"BA", X"0A", X"00", X"00", X"03", X"0A", X"00",
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X"00", X"02", X"04", X"00", X"04", X"00", X"00", X"1C",
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X"89", X"4D", X"00", X"01", X"02", X"03", X"04", X"05",
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X"06", X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D",
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X"0E", X"0F", X"10", X"11", X"12", X"13"
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);
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BEGIN
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inst_crc32: entity work.crc32
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PORT MAP
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(
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rst => RST,
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clk => CLK,
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din_vld => din_vld,
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din => din,
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crc32_vld => crc32_vld,
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crc32_out => crc32
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);
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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CLK <= not CLK;
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end process;
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-- Master
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STIMULUS: process
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begin
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wait for 6*CLK_PERIOD;
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RST <= '0';
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wait for 6*CLK_PERIOD;
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wait until rising_edge(CLK);
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for i in 0 to 61 loop
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din_vld <= '1';
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din <= test_data(i);
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wait until rising_edge(CLK);
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end loop;
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din <= (others => '-');
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din_vld <= '0';
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wait;
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end process;
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END;
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