-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: testbench for system test using Xilinx ML-402

-- Copyright (C) 2007 J. Ahrensfeld

-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.

-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-- Lesser General Public License for more details.

-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA

-- For questions and ideas, please contact the author at jens@jayfield.org

-----------------------------------------------------------------------

LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY tb_crc32 IS
END tb_crc32;

ARCHITECTURE behavior OF tb_crc32 IS 

	constant CLK_PERIOD		: time := 10 ns;

	signal CLK				: std_logic := '1';
	signal RST				: std_logic := '1';

	signal din_vld			: std_logic := '0';
	signal din				: unsigned(7 downto 0) := (others => '-');
	signal crc32			: unsigned(31 downto 0);
	signal crc32_vld		: std_logic;


	type byte_array_t is array (0 to 61) of unsigned(7 downto 0);
	
	signal test_data : byte_array_t :=
	(
		X"00", X"0A", X"E6", X"F0", X"05", X"A3", X"00", X"12",
		X"34", X"56", X"78", X"90", X"08", X"00", X"45", X"00",
		X"00", X"30", X"B3", X"FE", X"00", X"00", X"80", X"11",
		X"72", X"BA", X"0A", X"00", X"00", X"03", X"0A", X"00",
		X"00", X"02", X"04", X"00", X"04", X"00", X"00", X"1C",
		X"89", X"4D", X"00", X"01", X"02", X"03", X"04", X"05",
		X"06", X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D",
		X"0E", X"0F", X"10", X"11", X"12", X"13"
	);
	
BEGIN

inst_crc32: entity work.crc32
	PORT MAP
	(
		rst				=> RST,
		clk				=> CLK,
		din_vld			=> din_vld,
		din				=> din,
		crc32_vld		=> crc32_vld,
		crc32_out		=> crc32
		
	);


CLK_GEN: process
	begin
		wait for CLK_PERIOD/2;
		CLK <= not CLK;
	end process;


-- Master
STIMULUS: process


	begin

		wait for 6*CLK_PERIOD;
		RST <= '0';
		wait for 6*CLK_PERIOD;

		wait until rising_edge(CLK);

		for i in 0 to 61 loop
			din_vld	<= '1';
			din		<= test_data(i);
			wait until rising_edge(CLK);
		end loop;

		din		<= (others => '-');
		din_vld	<= '0';

		wait; 
	
	end process;
	
END;