jens 5f29361ee4 - added vld_pipe flush during reset ...

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git-svn-id: http://moon:8086/svn/vhdl/trunk@804 cc03376c-175c-47c8-b038-4cd826a8556b

2010-03-21 11:35:33 +00:00

..

ac97_ctrl

- renamed fifo_*sync_ctrl

2009-01-30 21:30:21 +00:00

CPUs

- increased revision to R13

2010-03-13 16:49:12 +00:00

emac

- added vld_pipe flush during reset

2010-03-21 11:35:33 +00:00

FIFO

- cleaned up

2010-02-13 10:51:47 +00:00

filter

- renamed fifo_*sync_ctrl

2009-01-30 21:30:21 +00:00

fix_std

Initial import

2008-08-23 08:20:30 +00:00

fixed

deleted

2009-01-11 15:31:42 +00:00

fixed_ja

Initial import

2008-08-23 08:20:30 +00:00

jasm

Initial import

2008-08-23 08:20:30 +00:00

misc

- made GPIO 0 bidirectional (added GPIO_DIR register)

2010-03-13 16:46:21 +00:00

PCK_FIO-1.16

Minor changes

2010-03-12 07:35:21 +00:00

PCK_FIO-2002.7

Initial import

2008-08-23 08:20:30 +00:00

ps2_port

- fixed rounding issue in usec prescaler

2010-02-09 11:46:08 +00:00

radio

Minor changes

2010-03-12 07:41:31 +00:00

SDRAM

Minor changes to max cycle count

2010-02-09 09:56:44 +00:00

SSRAM

- Using MODELSIM_HOME environment variable

2008-10-23 21:21:24 +00:00

uart

- added generic 'simulate_tx' for output of TX-Data into simulation log

2010-03-07 16:10:57 +00:00

VGA_ctrl

- added new FIFO generics

2010-02-12 10:36:50 +00:00