jens
bdb8fec295
git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b
159 lines
4.4 KiB
Plaintext
159 lines
4.4 KiB
Plaintext
images.vhdl
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Package specification for images.
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images-body.vhdl
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Package body for images.
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images_test.vhdl
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Entity declaration for test bench for images package.
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images_test-bench.vhdl
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Architecture body for test bench for images package.
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bv_arithmetic.vhdl
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Package specification for bit vector conversions and arithmetic
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bv_arithmetic-body.vhdl
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Package body for bit vector conversions and arithmetic
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bv_test.vhdl
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Entity declaration for test bench for bit vector arithmetic package
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bv_test-bench.vhdl
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Architecture for test bench for bit vector arithmetic package
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----------------------------------------------------------------
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clock_gen.vhdl
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Entity declaration for clock generator
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clock_gen-behaviour.vhdl
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Behavioural architecture body for clock generator
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clock_gen_test.vhdl
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Entity declaration for test bench for clock generator
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clock_gen_test-bench.vhdl
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Architecture for test bench for clock generator
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dlx_types.vhdl
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Package specification for types used in dlx model
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dlx_types-body.vhdl
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Package body for types used in dlx model
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mem_types.vhdl
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Types package for memory model
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memory.vhdl
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Entity declaration for memory model
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memory-behaviour.vhdl
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Behavioural architecture for memory model
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memory_test.vhdl
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Entity declaration for test bench for memory
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memory_test-bench.vhdl
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Architecture for test bench for behavioural architecture of memory
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dlx_instr.vhdl
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Package specification for DLX instructions
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dlx_instr-body.vhdl
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Package body for DLX instructions
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dlx_bus_monitor.vhdl
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Entity declaration of DLX bus monitor
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dlx_bus_monitor-behaviour.vhdl
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Behavioural architecture of DLX bus monitor
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dlx_test.vhdl
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Entity declaration for test bench for DLX
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dlx_test-bench.vhdl
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Architecture for test bench for DLX,
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consisting of clock generator, memory and bus_monitor
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dlx.vhdl
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Entity specification for DLX processor
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dlx-behaviour.vhdl
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Behavioural architecture for DLX processor
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dlx_test_behaviour.vhdl
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Configuration of test bench for DLX, using architecture behaviour
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dlx-instrumented.vhdl
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Instrumented behavioural architecture for DLX, that generates
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a files of instruction execution frequencies for a program.
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dlx_test_instrumented.vhdl
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Configuration of test bench for DLX, using instrumented
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architecture of CPU and empty architecture of bus monitor.
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----------------------------------------------------------------
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alu_types.vhdl
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Package defining types for ALU.
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alu.vhdl
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Entity declaration for ALU.
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alu-behaviour.vhdl
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Behavioural architecture of ALU.
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ir.vhdl
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Entity declaration for instruction register.
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ir-behaviour.vhdl
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Behavioural architecture of instruction register.
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latch.vhdl
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Entity declaration for transparent latch.
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latch-behaviour.vhdl
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Behavioural architecture of transparent latch.
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mux2.vhdl
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Entity declaration for two-input multiplexor.
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mux2-behaviour.vhdl
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Behavioural architecture of two-input multiplexor.
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reg_1_out.vhdl
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Entity declaration for register with one tri-state output.
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reg_1_out-behaviour.vhdl
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Behavioural architecture of register with one tri-state output.
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reg_2_1_out.vhdl
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Entity declaration for register with two tri-state outputs and
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one ordinary output.
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reg_2_1_out-behaviour.vhdl
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Behavioural architecture of register with two tri-state
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outputs and one ordinary output.
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reg_2_out.vhdl
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Entity declaration for register with two tri-state outputs.
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reg_2_out-behaviour.vhdl
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Behavioural architecture of register with two tri-state outputs.
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reg_3_out.vhdl
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Entity declaration for register with three tri-state outputs.
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reg_3_out-behaviour.vhdl
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Behavioural architecture of register with three tri-state outputs.
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reg_file.vhdl
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Entity declaration for register file.
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reg_file-behaviour.vhdl
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Behavioural architecture of register file.
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controller.vhdl
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Entity declaration for DLX control section.
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controller-behaviour.vhdl
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Behavioural architecture of DLX control section.
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dlx-rtl.vhdl
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Register transfer level architecture of DLX processor.
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dlx_test_rtl.vhdl
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Configuration of DLX test bench using register transfer level
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architecture of DLX processor.
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----------------------------------------------------------------
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cache_types.vhdl
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Package spec defining types for cache.
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cache.vhdl
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Entity declaration for cache.
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cache-behaviour.vhdl
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Behavioural architecture for cache.
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dlx_test-bench_cache.vhdl
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Architecture for test bench for DLX and cache,
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including clock generator, memory and bus monitors for
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both CPU/cache and cache/memory buses.
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dlx_test_cache.vhdl
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Configuration of test bench for DLX and cache,
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using behavioural architectures.
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