jens
bdb8fec295
git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b
55 lines
2.2 KiB
VHDL
55 lines
2.2 KiB
VHDL
--------------------------------------------------------------------------
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--
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-- Copyright (C) 1993, Peter J. Ashenden
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-- Mail: Dept. Computer Science
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-- University of Adelaide, SA 5005, Australia
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-- e-mail: petera@cs.adelaide.edu.au
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 1, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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--
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--------------------------------------------------------------------------
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--
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-- $RCSfile: memory.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 21:09:12 $
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--
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--------------------------------------------------------------------------
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--
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-- Entity declaration for memory model
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--
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use work.dlx_types.all, work.mem_types.all;
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entity memory is
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generic (mem_size : positive; -- size in bytes (multiple of 4)
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Tac1 : Time; -- access time 1st cycle (read or write)
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Tacb : Time; -- access time burst (read or write)
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Tpd_clk_out : Time; -- clock to output delay
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tag : string := "";
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origin_x, origin_y : real := 0.0);
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port (phi1, phi2 : in bit; -- 2-phase non-overlapping clocks
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a : in dlx_address; -- byte address: a(0) is lsb
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d : inout dlx_word_bus bus; -- bidirectional data bus: d(0) is msb
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width : in mem_width; -- byte/haldword/word indicator
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write_enable : in bit; -- selects read or write cycle
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burst : in bit := '0'; -- indicates more to come in burst
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-- can be left open
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-- for non-burst client
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mem_enable : in bit; -- starts memory cycle
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ready : out bit); -- status from memory system
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end memory;
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