jens
8a1836039c
git-svn-id: http://moon:8086/svn/vhdl/trunk@1055 cc03376c-175c-47c8-b038-4cd826a8556b
70 lines
1.9 KiB
VHDL
70 lines
1.9 KiB
VHDL
--------------------------------------------------------------------------
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-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
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-- This file: On-Chip work registers
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--
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-- Copyright (C) 2008 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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use work.mips_types.all;
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entity dpram_1w1r1wc is
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Generic
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(
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addr_width : integer := 3;
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data_width : integer := 8
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);
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Port
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(
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clk_w : in STD_LOGIC;
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we : in STD_LOGIC;
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wptr : in unsigned (addr_width-1 downto 0);
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rptr : in unsigned (addr_width-1 downto 0);
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din : in unsigned (data_width-1 downto 0);
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dout : out unsigned (data_width-1 downto 0)
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);
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end dpram_1w1r1wc;
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architecture Behavioral of dpram_1w1r1wc is
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constant depth : integer := 2**addr_width;
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type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0);
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signal mem : mem_t;
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begin
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reg_in:
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process(clk_w)
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begin
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if rising_edge(clk_w) then
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if we = '1' then
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mem(to_integer(wptr)) <= din;
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end if;
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end if;
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end process;
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dout <= mem(to_integer(rptr));
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end Behavioral;
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