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git-svn-id: http://moon:8086/svn/vhdl/trunk@1055 cc03376c-175c-47c8-b038-4cd826a8556b

lib/rams/dpram_1w1r1wc_sim.vhd

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+--------------------------------------------------------------------------
+-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
+-- This file: On-Chip work registers
+--
+-- Copyright (C) 2008 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.mips_types.all;
+
+entity dpram_1w1r1wc is
+	Generic
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port
+	(
+		clk_w		: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		wptr		: in  unsigned (addr_width-1 downto 0);
+		rptr		: in  unsigned (addr_width-1 downto 0);
+		din			: in  unsigned (data_width-1 downto 0);
+		dout		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_1w1r1wc;
+
+architecture Behavioral of dpram_1w1r1wc is
+
+	constant depth : integer := 2**addr_width;
+	type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+
+	signal mem : mem_t;
+	
+begin
+
+reg_in:
+	process(clk_w)
+	begin
+		if rising_edge(clk_w) then
+			if we = '1' then
+				mem(to_integer(wptr)) <= din;
+			end if;
+		end if;	
+	end process;
+
+	dout <= mem(to_integer(rptr));
+
+end Behavioral;
+

lib/rams/dpram_x1w1r2c_ra_xil.vhd

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+-------------------------------------------------------------------------
+-- Project: Dual-Port RAM with 1 clock latency for simulation
+-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered address
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+entity dpram_x1w1r2c_ra is
+	Generic 
+	(
+		addr_width_a : integer := 10;
+		addr_width_b : integer := 10;
+		data_width_a : integer := 32;
+		data_width_b : integer := 32
+	);
+	Port
+	(
+		clk_a		: in  STD_LOGIC;
+		clk_b		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width_a-1 downto 0);
+		addr_b		: in  unsigned (addr_width_b-1 downto 0);
+		din_a		: in  unsigned (data_width_a-1 downto 0);
+		dout_b		: out unsigned (data_width_b-1 downto 0)
+	);
+end dpram_x1w1r2c_ra;
+
+architecture Behavioral of dpram_x1w1r2c_ra is
+
+	constant NUM_RAM_INSTANCES : integer := data_width_a;
+	
+begin
+
+gen_rams:
+for i in 0 to NUM_RAM_INSTANCES-1 generate
+
+inst_dpram_1w1r2c_ra: entity work.dpram_1w1r2c_ra
+	GENERIC MAP 
+	(
+		addr_width	=>	addr_width_a,
+		data_width	=>	1
+	)
+	PORT MAP 
+	(
+		clk_a	=>	clk_a,
+		clk_b	=>	clk_b,
+		en_a	=>	'1',
+		en_b	=>	en_b,
+		we_a	=>	we_a,
+		addr_a	=>	addr_a,
+		addr_b	=>	addr_b,
+		din_a	=>	din_a(i downto i),
+		dout_b	=>	dout_b(i downto i)
+	);
+
+end generate;
+
+end Behavioral;
+