jens
bdb8fec295
git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b
45 lines
1.5 KiB
VHDL
45 lines
1.5 KiB
VHDL
--------------------------------------------------------------------------
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--
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-- Copyright (C) 1993, Peter J. Ashenden
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-- Mail: Dept. Computer Science
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-- University of Adelaide, SA 5005, Australia
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-- e-mail: petera@cs.adelaide.edu.au
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 1, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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--
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--------------------------------------------------------------------------
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--
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-- $RCSfile: reg_2_1_out.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 19:06:47 $
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--
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--------------------------------------------------------------------------
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--
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-- Entity declaration for register with two tri-state outputs and
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-- one ordinary output.
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--
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use work.dlx_types.all;
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entity reg_2_1_out is
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generic (Tpd : Time;
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tag : string := "";
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origin_x, origin_y : real := 0.0);
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port (d : in dlx_word;
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q1, q2 : out dlx_word_bus bus;
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q3 : out dlx_word;
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latch_en : in bit;
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out_en1, out_en2 : in bit);
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end reg_2_1_out;
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