jens 55b8103189 - reduced sim time ...

git-svn-id: http://moon:8086/svn/vhdl/trunk@1450 cc03376c-175c-47c8-b038-4cd826a8556b

2021-03-22 17:10:22 +00:00

Common

- fixed WORK_DIR

2021-03-22 08:22:06 +00:00

lib

- reduced sim time

2021-03-22 17:10:22 +00:00

projects

- fixed ghdl.mk

2021-03-21 18:16:11 +00:00

S

Description

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23 MiB

Languages

VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%