jens
bdb8fec295
git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b
104 lines
3.2 KiB
VHDL
104 lines
3.2 KiB
VHDL
--------------------------------------------------------------------------
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--
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-- Copyright (C) 1993, Peter J. Ashenden
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-- Mail: Dept. Computer Science
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-- University of Adelaide, SA 5005, Australia
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-- e-mail: petera@cs.adelaide.edu.au
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 1, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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--
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--------------------------------------------------------------------------
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--
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-- $RCSfile: dlx_test_rtl.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 20:20:00 $
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--
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--------------------------------------------------------------------------
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--
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-- Configuration of DLX test bench using register transfer level
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-- architecture of DLX processor.
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--
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configuration dlx_test_rtl of dlx_test is
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for bench
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for cg : clock_gen
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use entity work.clock_gen(behaviour)
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generic map (Tpw => 8 ns, Tps => 2 ns);
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end for;
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for mem : memory
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use entity work.memory(behaviour)
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generic map (mem_size => 65536,
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Tac1 => 95 ns, Tacb => 35 ns, Tpd_clk_out => 2 ns);
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end for;
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for bus_monitor : dlx_bus_monitor
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use entity work.dlx_bus_monitor(behaviour)
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generic map (enable => true, verbose => true, tag => "bus monitor");
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end for;
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for proc : dlx
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use entity work.dlx(rtl)
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generic map (Tpd_clk_out => 2 ns, debug => true, tag => "proc");
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for rtl
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for all : alu
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use entity work.alu(behaviour)
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generic map (Tpd => 4 ns);
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end for;
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for all : reg_file
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use entity work.reg_file(behaviour)
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generic map (Tac => 4 ns);
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end for;
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for all : latch
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use entity work.latch(behaviour)
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generic map (Tpd => 2 ns);
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end for;
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for all : reg_1_out
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use entity work.reg_1_out(behaviour)
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generic map (Tpd => 2 ns);
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end for;
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for all : reg_2_out
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use entity work.reg_2_out(behaviour)
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generic map (Tpd => 2 ns);
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end for;
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for all : reg_2_1_out
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use entity work.reg_2_1_out(behaviour)
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generic map (Tpd => 2 ns);
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end for;
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for all : reg_3_out
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use entity work.reg_3_out(behaviour)
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generic map (Tpd => 2 ns);
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end for;
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for all : mux2
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use entity work.mux2(behaviour)
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generic map (Tpd => 1 ns);
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end for;
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for all : ir
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use entity work.ir(behaviour)
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generic map (Tpd => 2 ns);
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end for;
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for the_controller : controller
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use entity work.controller(behaviour)
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generic map (Tpd_clk_ctrl => 2 ns, Tpd_clk_const => 4 ns,
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debug => true);
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end for;
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end for; -- rtl of dlx
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end for; -- proc : dlx
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end for; -- bench of dlx_test
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end dlx_test_rtl;
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