jens
bdb8fec295
git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b
859 lines
29 KiB
VHDL
859 lines
29 KiB
VHDL
--------------------------------------------------------------------------
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--
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-- Copyright (C) 1993, Peter J. Ashenden
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-- Mail: Dept. Computer Science
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-- University of Adelaide, SA 5005, Australia
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-- e-mail: petera@cs.adelaide.edu.au
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 1, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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--
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--------------------------------------------------------------------------
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--
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-- $RCSfile: controller-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 21:36:38 $
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--
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--------------------------------------------------------------------------
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--
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-- Behavioural architecture of DLX control section.
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--
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use work.bv_arithmetic.all, std.textio.all;
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architecture behaviour of controller is
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begin -- behaviour
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sequencer : process
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alias IR_opcode : dlx_opcode is current_instruction(0 to 5);
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alias IR_sp_func : dlx_sp_func is current_instruction(26 to 31);
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alias IR_fp_func : dlx_fp_func is current_instruction(27 to 31);
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alias IR_rs1 : dlx_reg_addr is current_instruction(6 to 10);
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alias IR_rs2 : dlx_reg_addr is current_instruction(11 to 15);
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alias IR_Itype_rd : dlx_reg_addr is current_instruction(11 to 15);
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alias IR_Rtype_rd : dlx_reg_addr is current_instruction(16 to 20);
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alias IR_immed16 : dlx_immed16 is current_instruction(16 to 31);
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alias IR_immed26 : dlx_immed26 is current_instruction(6 to 31);
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variable IR_opcode_num : dlx_opcode_num;
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variable IR_sp_func_num : dlx_sp_func_num;
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variable IR_fp_func_num : dlx_fp_func_num;
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variable result_of_set_is_1, branch_taken : boolean;
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variable L : line;
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procedure bus_instruction_fetch is
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begin
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-- use PC as address
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mem_addr_mux_sel <= '0' after Tpd_clk_ctrl;
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-- set up memory control signals
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width <= width_word after Tpd_clk_ctrl;
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ifetch <= '1' after Tpd_clk_ctrl;
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mem_enable <= '1' after Tpd_clk_ctrl;
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-- wait until phi2, then enable IR input
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wait until phi2 = '1';
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ir_latch_en <= '1' after Tpd_clk_ctrl;
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-- wait until memory is ready at end of phi2
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loop
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wait until phi2 = '0';
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if reset = '1' then
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return;
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end if;
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exit when ready = '1';
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end loop;
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-- disable IR input and memory control signals
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ir_latch_en <= '0' after Tpd_clk_ctrl;
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mem_enable <= '0' after Tpd_clk_ctrl;
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end bus_instruction_fetch;
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procedure bus_data_read(read_width : in mem_width) is
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begin
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-- use MAR as address
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mem_addr_mux_sel <= '1' after Tpd_clk_ctrl;
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-- set up memory control signals
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width <= read_width after Tpd_clk_ctrl;
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ifetch <= '0' after Tpd_clk_ctrl;
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mem_enable <= '1' after Tpd_clk_ctrl;
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-- wait until phi2, then enable MDR input
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wait until phi2 = '1';
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mdr_mux_sel <= '1' after Tpd_clk_ctrl;
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mdr_latch_en <= '1' after Tpd_clk_ctrl;
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-- wait until memory is ready at end of phi2
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loop
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wait until phi2 = '0';
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if reset = '1' then
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return;
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end if;
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exit when ready = '1';
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end loop;
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-- disable MDR input and memory control signals
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mdr_latch_en <= '0' after Tpd_clk_ctrl;
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mem_enable <= '0' after Tpd_clk_ctrl;
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end bus_data_read;
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procedure bus_data_write(write_width : in mem_width) is
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begin
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-- use MAR as address
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mem_addr_mux_sel <= '1' after Tpd_clk_ctrl;
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-- enable MDR output
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mdr_out_en3 <= '1' after Tpd_clk_ctrl;
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-- set up memory control signals
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width <= write_width after Tpd_clk_ctrl;
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ifetch <= '0' after Tpd_clk_ctrl;
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write_enable <= '1' after Tpd_clk_ctrl;
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mem_enable <= '1' after Tpd_clk_ctrl;
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-- wait until memory is ready at end of phi2
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loop
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wait until phi2 = '0';
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if reset = '1' then
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return;
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end if;
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exit when ready = '1';
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end loop;
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-- disable MDR output and memory control signals
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write_enable <= '0' after Tpd_clk_ctrl;
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mem_enable <= '0' after Tpd_clk_ctrl;
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mdr_out_en3 <= '0' after Tpd_clk_ctrl;
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end bus_data_write;
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procedure do_set_result is
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begin
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wait until phi1 = '1';
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if result_of_set_is_1 then
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const2 <= X"0000_0001" after Tpd_clk_const;
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else
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const2 <= X"0000_0000" after Tpd_clk_const;
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end if;
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alu_latch_en <= '1' after Tpd_clk_ctrl;
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alu_function <= alu_pass_s2 after Tpd_clk_ctrl;
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--
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wait until phi1 = '0';
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alu_latch_en <= '0' after Tpd_clk_ctrl;
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const2 <= null after Tpd_clk_const;
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--
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wait until phi2 = '1';
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c_latch_en <= '1' after Tpd_clk_ctrl;
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--
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wait until phi2 = '0';
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c_latch_en <= '0' after Tpd_clk_ctrl;
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end do_set_result;
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procedure do_EX_set_unsigned(immed : boolean) is
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begin
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wait until phi1 = '1';
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a_out_en <= '1' after Tpd_clk_ctrl;
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if immed then
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ir_immed_sel2 <= immed_size_16 after Tpd_clk_ctrl;
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ir_immed_unsigned2 <= '1' after Tpd_clk_ctrl;
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ir_immed_en2 <= '1' after Tpd_clk_ctrl;
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else
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b_out_en <= '1' after Tpd_clk_ctrl;
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end if;
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alu_latch_en <= '1' after Tpd_clk_ctrl;
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alu_function <= alu_subu after Tpd_clk_ctrl;
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--
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wait until phi1 = '0';
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alu_latch_en <= '0' after Tpd_clk_ctrl;
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a_out_en <= '0' after Tpd_clk_ctrl;
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if immed then
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ir_immed_en2 <= '0' after Tpd_clk_ctrl;
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else
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b_out_en <= '0' after Tpd_clk_ctrl;
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end if;
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--
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wait until phi2 = '0';
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if immed then
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case IR_opcode is
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when op_sequi =>
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result_of_set_is_1 := alu_zero = '1';
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when op_sneui =>
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result_of_set_is_1 := alu_zero /= '1';
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when op_sltui =>
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result_of_set_is_1 := alu_overflow = '1';
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when op_sgtui =>
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result_of_set_is_1 := alu_overflow /= '1' and alu_zero /= '1';
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when op_sleui =>
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result_of_set_is_1 := alu_overflow = '1' or alu_zero = '1';
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when op_sgeui =>
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result_of_set_is_1 := alu_overflow /= '1';
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when others =>
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null;
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end case;
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else
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case IR_sp_func is
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when sp_func_sequ =>
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result_of_set_is_1 := alu_zero = '1';
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when sp_func_sneu =>
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result_of_set_is_1 := alu_zero /= '1';
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when sp_func_sltu =>
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result_of_set_is_1 := alu_overflow = '1';
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when sp_func_sgtu =>
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result_of_set_is_1 := alu_overflow /= '1' and alu_zero /= '1';
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when sp_func_sleu =>
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result_of_set_is_1 := alu_overflow = '1' or alu_zero = '1';
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when sp_func_sgeu =>
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result_of_set_is_1 := alu_overflow /= '1';
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when others =>
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null;
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end case;
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end if;
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--
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do_set_result;
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end do_EX_set_unsigned;
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procedure do_EX_set_signed(immed : boolean) is
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begin
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wait until phi1 = '1';
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a_out_en <= '1' after Tpd_clk_ctrl;
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if immed then
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ir_immed_sel2 <= immed_size_16 after Tpd_clk_ctrl;
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ir_immed_unsigned2 <= '0' after Tpd_clk_ctrl;
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ir_immed_en2 <= '1' after Tpd_clk_ctrl;
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else
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b_out_en <= '1' after Tpd_clk_ctrl;
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end if;
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alu_latch_en <= '1' after Tpd_clk_ctrl;
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alu_function <= alu_sub after Tpd_clk_ctrl;
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--
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wait until phi1 = '0';
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alu_latch_en <= '0' after Tpd_clk_ctrl;
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a_out_en <= '0' after Tpd_clk_ctrl;
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if immed then
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ir_immed_en2 <= '0' after Tpd_clk_ctrl;
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else
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b_out_en <= '0' after Tpd_clk_ctrl;
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end if;
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--
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wait until phi2 = '0';
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if immed then
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case IR_opcode is
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when op_seqi =>
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result_of_set_is_1 := alu_zero = '1';
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when op_snei =>
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result_of_set_is_1 := alu_zero /= '1';
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when op_slti =>
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result_of_set_is_1 := alu_negative = '1';
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when op_sgti =>
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result_of_set_is_1 := alu_negative /= '1' and alu_zero /= '1';
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when op_slei =>
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result_of_set_is_1 := alu_negative = '1' or alu_zero = '1';
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when op_sgei =>
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result_of_set_is_1 := alu_negative /= '1';
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when others =>
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null;
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end case;
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else
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case IR_sp_func is
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when sp_func_seq =>
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result_of_set_is_1 := alu_zero = '1';
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when sp_func_sne =>
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result_of_set_is_1 := alu_zero /= '1';
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when sp_func_slt =>
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result_of_set_is_1 := alu_negative = '1';
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when sp_func_sgt =>
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result_of_set_is_1 := alu_negative /= '1' and alu_zero /= '1';
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when sp_func_sle =>
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result_of_set_is_1 := alu_negative = '1' or alu_zero = '1';
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when sp_func_sge =>
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result_of_set_is_1 := alu_negative /= '1';
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when others =>
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null;
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end case;
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end if;
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--
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do_set_result;
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end do_EX_set_signed;
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procedure do_EX_arith_logic is
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begin
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wait until phi1 = '1';
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a_out_en <= '1' after Tpd_clk_ctrl;
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b_out_en <= '1' after Tpd_clk_ctrl;
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alu_latch_en <= '1' after Tpd_clk_ctrl;
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case IR_sp_func is
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when sp_func_add =>
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alu_function <= alu_add after Tpd_clk_ctrl;
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when sp_func_addu =>
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alu_function <= alu_addu after Tpd_clk_ctrl;
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when sp_func_sub =>
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alu_function <= alu_sub after Tpd_clk_ctrl;
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when sp_func_subu =>
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alu_function <= alu_subu after Tpd_clk_ctrl;
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when sp_func_and =>
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alu_function <= alu_and after Tpd_clk_ctrl;
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when sp_func_or =>
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alu_function <= alu_or after Tpd_clk_ctrl;
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when sp_func_xor =>
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alu_function <= alu_xor after Tpd_clk_ctrl;
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when sp_func_sll =>
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alu_function <= alu_sll after Tpd_clk_ctrl;
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when sp_func_srl =>
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alu_function <= alu_srl after Tpd_clk_ctrl;
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when sp_func_sra =>
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alu_function <= alu_sra after Tpd_clk_ctrl;
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when others =>
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null;
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end case; -- IR_sp_func
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--
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wait until phi1 = '0';
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alu_latch_en <= '0' after Tpd_clk_ctrl;
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a_out_en <= '0' after Tpd_clk_ctrl;
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b_out_en <= '0' after Tpd_clk_ctrl;
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--
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wait until phi2 = '1';
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c_latch_en <= '1' after Tpd_clk_ctrl;
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--
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wait until phi2 = '0';
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c_latch_en <= '0' after Tpd_clk_ctrl;
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end do_EX_arith_logic;
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procedure do_EX_arith_logic_immed is
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begin
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wait until phi1 = '1';
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a_out_en <= '1' after Tpd_clk_ctrl;
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ir_immed_sel2 <= immed_size_16 after Tpd_clk_ctrl;
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if IR_opcode = op_addi or IR_opcode = op_subi then
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ir_immed_unsigned2 <= '0' after Tpd_clk_ctrl;
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else
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ir_immed_unsigned2 <= '1' after Tpd_clk_ctrl;
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end if;
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ir_immed_en2 <= '1' after Tpd_clk_ctrl;
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alu_latch_en <= '1' after Tpd_clk_ctrl;
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case IR_opcode is
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when op_addi =>
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alu_function <= alu_add after Tpd_clk_ctrl;
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when op_subi =>
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alu_function <= alu_sub after Tpd_clk_ctrl;
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when op_addui =>
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alu_function <= alu_addu after Tpd_clk_ctrl;
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when op_subui =>
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alu_function <= alu_subu after Tpd_clk_ctrl;
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when op_andi =>
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alu_function <= alu_and after Tpd_clk_ctrl;
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when op_ori =>
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alu_function <= alu_or after Tpd_clk_ctrl;
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when op_xori =>
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alu_function <= alu_xor after Tpd_clk_ctrl;
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when op_slli =>
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alu_function <= alu_sll after Tpd_clk_ctrl;
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when op_srli =>
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alu_function <= alu_srl after Tpd_clk_ctrl;
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when op_srai =>
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alu_function <= alu_sra after Tpd_clk_ctrl;
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when others =>
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null;
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end case; -- IR_opcode
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--
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wait until phi1 = '0';
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alu_latch_en <= '0' after Tpd_clk_ctrl;
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a_out_en <= '0' after Tpd_clk_ctrl;
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ir_immed_en2 <= '0' after Tpd_clk_ctrl;
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--
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wait until phi2 = '1';
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c_latch_en <= '1' after Tpd_clk_ctrl;
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--
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wait until phi2 = '0';
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c_latch_en <= '0' after Tpd_clk_ctrl;
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end do_EX_arith_logic_immed;
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procedure do_EX_link is
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begin
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wait until phi1 = '1';
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pc_out_en1 <= '1' after Tpd_clk_ctrl;
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alu_latch_en <= '1' after Tpd_clk_ctrl;
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alu_function <= alu_pass_s1 after Tpd_clk_ctrl;
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--
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wait until phi1 = '0';
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alu_latch_en <= '0' after Tpd_clk_ctrl;
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pc_out_en1 <= '0' after Tpd_clk_ctrl;
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--
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wait until phi2 = '1';
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c_latch_en <= '1' after Tpd_clk_ctrl;
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--
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wait until phi2 = '0';
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c_latch_en <= '0' after Tpd_clk_ctrl;
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end do_EX_link;
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procedure do_EX_lhi is
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begin
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wait until phi1 = '1';
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ir_immed_sel1 <= immed_size_16 after Tpd_clk_ctrl;
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ir_immed_unsigned1 <= '1' after Tpd_clk_ctrl;
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ir_immed_en1 <= '1' after Tpd_clk_ctrl;
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const2 <= X"0000_0010" after Tpd_clk_const; -- shift by 16 bits
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alu_latch_en <= '1' after Tpd_clk_ctrl;
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alu_function <= alu_sll after Tpd_clk_ctrl;
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--
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wait until phi1 = '0';
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alu_latch_en <= '0' after Tpd_clk_ctrl;
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ir_immed_en1 <= '0' after Tpd_clk_ctrl;
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const2 <= null after Tpd_clk_const;
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--
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wait until phi2 = '1';
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c_latch_en <= '1' after Tpd_clk_ctrl;
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--
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wait until phi2 = '0';
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c_latch_en <= '0' after Tpd_clk_ctrl;
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end do_EX_lhi;
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procedure do_EX_branch is
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begin
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wait until phi1 = '1';
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a_out_en <= '1' after Tpd_clk_ctrl;
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const2 <= X"0000_0000" after Tpd_clk_const;
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alu_latch_en <= '1' after Tpd_clk_ctrl;
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alu_function <= alu_sub after Tpd_clk_ctrl;
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--
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wait until phi1 = '0';
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alu_latch_en <= '0' after Tpd_clk_ctrl;
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a_out_en <= '0' after Tpd_clk_ctrl;
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const2 <= null after Tpd_clk_const;
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--
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wait until phi2 = '0';
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if IR_opcode = op_beqz then
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branch_taken := alu_zero = '1';
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else
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branch_taken := alu_zero /= '1';
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end if;
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end do_EX_branch;
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procedure do_EX_load_store is
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begin
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wait until phi1 = '1';
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a_out_en <= '1' after Tpd_clk_ctrl;
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ir_immed_sel2 <= immed_size_16 after Tpd_clk_ctrl;
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ir_immed_unsigned2 <= '0' after Tpd_clk_ctrl;
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ir_immed_en2 <= '1' after Tpd_clk_ctrl;
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alu_function <= alu_add after Tpd_clk_ctrl;
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alu_latch_en <= '1' after Tpd_clk_ctrl;
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--
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wait until phi1 = '0';
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alu_latch_en <= '0' after Tpd_clk_ctrl;
|
|
a_out_en <= '0' after Tpd_clk_ctrl;
|
|
ir_immed_en2 <= '0' after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi2 = '1';
|
|
mar_latch_en <= '1' after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi2 = '0';
|
|
mar_latch_en <= '0' after Tpd_clk_ctrl;
|
|
end do_EX_load_store;
|
|
|
|
procedure do_MEM_jump is
|
|
begin
|
|
wait until phi1 = '1';
|
|
pc_out_en1 <= '1' after Tpd_clk_ctrl;
|
|
ir_immed_sel2 <= immed_size_26 after Tpd_clk_ctrl;
|
|
ir_immed_unsigned2 <= '0' after Tpd_clk_ctrl;
|
|
ir_immed_en2 <= '1' after Tpd_clk_ctrl;
|
|
alu_latch_en <= '1' after Tpd_clk_ctrl;
|
|
alu_function <= alu_add after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi1 = '0';
|
|
alu_latch_en <= '0' after Tpd_clk_ctrl;
|
|
pc_out_en1 <= '0' after Tpd_clk_ctrl;
|
|
ir_immed_en2 <= '0' after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi2 = '1';
|
|
pc_latch_en <= '1' after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi2 = '0';
|
|
pc_latch_en <= '0' after Tpd_clk_ctrl;
|
|
end do_MEM_jump;
|
|
|
|
procedure do_MEM_jump_reg is
|
|
begin
|
|
wait until phi1 = '1';
|
|
a_out_en <= '1' after Tpd_clk_ctrl;
|
|
alu_latch_en <= '1' after Tpd_clk_ctrl;
|
|
alu_function <= alu_pass_s1 after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi1 = '0';
|
|
alu_latch_en <= '0' after Tpd_clk_ctrl;
|
|
a_out_en <= '0' after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi2 = '1';
|
|
pc_latch_en <= '1' after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi2 = '0';
|
|
pc_latch_en <= '0' after Tpd_clk_ctrl;
|
|
end do_MEM_jump_reg;
|
|
|
|
procedure do_MEM_branch is
|
|
begin
|
|
wait until phi1 = '1';
|
|
pc_out_en1 <= '1' after Tpd_clk_ctrl;
|
|
ir_immed_sel2 <= immed_size_16 after Tpd_clk_ctrl;
|
|
ir_immed_unsigned2 <= '0' after Tpd_clk_ctrl;
|
|
ir_immed_en2 <= '1' after Tpd_clk_ctrl;
|
|
alu_latch_en <= '1' after Tpd_clk_ctrl;
|
|
alu_function <= alu_add after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi1 = '0';
|
|
alu_latch_en <= '0' after Tpd_clk_ctrl;
|
|
pc_out_en1 <= '0' after Tpd_clk_ctrl;
|
|
ir_immed_en2 <= '0' after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi2 = '1';
|
|
pc_latch_en <= '1' after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi2 = '0';
|
|
pc_latch_en <= '0' after Tpd_clk_ctrl;
|
|
end do_MEM_branch;
|
|
|
|
procedure do_MEM_load is
|
|
begin
|
|
wait until phi1 = '1';
|
|
bus_data_read(width_word);
|
|
if reset = '1' then
|
|
return;
|
|
end if;
|
|
--
|
|
wait until phi1 = '1';
|
|
mdr_out_en1 <= '1' after Tpd_clk_ctrl;
|
|
alu_function <= alu_pass_s1 after Tpd_clk_ctrl;
|
|
alu_latch_en <= '1' after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi1 = '0';
|
|
mdr_out_en1 <= '0' after Tpd_clk_ctrl;
|
|
alu_latch_en <= '0' after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi2 = '1';
|
|
c_latch_en <= '1' after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi2 = '0';
|
|
c_latch_en <= '0' after Tpd_clk_ctrl;
|
|
end do_MEM_load;
|
|
|
|
procedure do_MEM_store is
|
|
begin
|
|
wait until phi1 = '1';
|
|
b_out_en <= '1' after Tpd_clk_ctrl;
|
|
alu_function <= alu_pass_s2 after Tpd_clk_ctrl;
|
|
alu_latch_en <= '1' after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi1 = '0';
|
|
b_out_en <= '0' after Tpd_clk_ctrl;
|
|
alu_latch_en <= '0' after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi2 = '1';
|
|
mdr_mux_sel <= '0' after Tpd_clk_ctrl;
|
|
mdr_latch_en <= '1' after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi2 = '0';
|
|
mdr_latch_en <= '0' after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi1 = '1';
|
|
bus_data_write(width_word);
|
|
end do_MEM_store;
|
|
|
|
procedure do_WB(Rd : dlx_reg_addr) is
|
|
begin
|
|
wait until phi1 = '1';
|
|
reg_dest_addr <= Rd after Tpd_clk_ctrl;
|
|
reg_write <= '1' after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi2 = '0';
|
|
reg_write <= '0' after Tpd_clk_ctrl;
|
|
end do_WB;
|
|
|
|
|
|
begin -- sequencer
|
|
--
|
|
----------------------------------------------------------------
|
|
-- initialize all control signals
|
|
----------------------------------------------------------------
|
|
if debug then
|
|
write(L, string'("controller: initializing"));
|
|
writeline(output, L);
|
|
end if;
|
|
--
|
|
halt <= '0' after Tpd_clk_ctrl;
|
|
width <= width_word after Tpd_clk_ctrl;
|
|
write_enable <= '0' after Tpd_clk_ctrl;
|
|
mem_enable <= '0' after Tpd_clk_ctrl;
|
|
ifetch <= '0' after Tpd_clk_ctrl;
|
|
alu_latch_en <= '0' after Tpd_clk_ctrl;
|
|
alu_function <= alu_add after Tpd_clk_ctrl;
|
|
reg_s1_addr <= B"00000" after Tpd_clk_ctrl;
|
|
reg_s2_addr <= B"00000" after Tpd_clk_ctrl;
|
|
reg_dest_addr <= B"00000" after Tpd_clk_ctrl;
|
|
reg_write <= '0' after Tpd_clk_ctrl;
|
|
c_latch_en <= '0' after Tpd_clk_ctrl;
|
|
a_latch_en <= '0' after Tpd_clk_ctrl;
|
|
a_out_en <= '0' after Tpd_clk_ctrl;
|
|
b_latch_en <= '0' after Tpd_clk_ctrl;
|
|
b_out_en <= '0' after Tpd_clk_ctrl;
|
|
temp_latch_en <= '0' after Tpd_clk_ctrl;
|
|
temp_out_en1 <= '0' after Tpd_clk_ctrl;
|
|
temp_out_en2 <= '0' after Tpd_clk_ctrl;
|
|
iar_latch_en <= '0' after Tpd_clk_ctrl;
|
|
iar_out_en1 <= '0' after Tpd_clk_ctrl;
|
|
iar_out_en2 <= '0' after Tpd_clk_ctrl;
|
|
pc_latch_en <= '0' after Tpd_clk_ctrl;
|
|
pc_out_en1 <= '0' after Tpd_clk_ctrl;
|
|
pc_out_en2 <= '0' after Tpd_clk_ctrl;
|
|
mar_latch_en <= '0' after Tpd_clk_ctrl;
|
|
mar_out_en1 <= '0' after Tpd_clk_ctrl;
|
|
mar_out_en2 <= '0' after Tpd_clk_ctrl;
|
|
mem_addr_mux_sel <= '0' after Tpd_clk_ctrl;
|
|
mdr_latch_en <= '0' after Tpd_clk_ctrl;
|
|
mdr_out_en1 <= '0' after Tpd_clk_ctrl;
|
|
mdr_out_en2 <= '0' after Tpd_clk_ctrl;
|
|
mdr_out_en3 <= '0' after Tpd_clk_ctrl;
|
|
mdr_mux_sel <= '0' after Tpd_clk_ctrl;
|
|
ir_latch_en <= '0' after Tpd_clk_ctrl;
|
|
ir_immed_sel1 <= immed_size_16 after Tpd_clk_ctrl;
|
|
ir_immed_sel2 <= immed_size_16 after Tpd_clk_ctrl;
|
|
ir_immed_unsigned1 <= '0' after Tpd_clk_ctrl;
|
|
ir_immed_unsigned2 <= '0' after Tpd_clk_ctrl;
|
|
ir_immed_en1 <= '0' after Tpd_clk_ctrl;
|
|
ir_immed_en2 <= '0' after Tpd_clk_ctrl;
|
|
const1 <= null after Tpd_clk_const;
|
|
const2 <= null after Tpd_clk_const;
|
|
--
|
|
wait until phi2 = '0' and reset = '0';
|
|
--
|
|
----------------------------------------------------------------
|
|
-- control loop
|
|
----------------------------------------------------------------
|
|
loop
|
|
--
|
|
----------------------------------------------------------------
|
|
-- fetch next instruction (IF)
|
|
----------------------------------------------------------------
|
|
wait until phi1 = '1';
|
|
if debug then
|
|
write(L, string'("controller: instruction fetch"));
|
|
writeline(output, L);
|
|
end if;
|
|
--
|
|
bus_instruction_fetch;
|
|
--
|
|
----------------------------------------------------------------
|
|
-- instruction decode, source register read, and PC increment (ID)
|
|
----------------------------------------------------------------
|
|
wait until phi1 = '1';
|
|
if debug then
|
|
write(L, string'("controller: decode, reg-read and PC incr"));
|
|
writeline(output, L);
|
|
end if;
|
|
--
|
|
IR_opcode_num := bv_to_natural(IR_opcode);
|
|
IR_sp_func_num := bv_to_natural(IR_sp_func);
|
|
IR_fp_func_num := bv_to_natural(IR_fp_func);
|
|
--
|
|
reg_s1_addr <= IR_rs1 after Tpd_clk_ctrl;
|
|
reg_s2_addr <= IR_rs2 after Tpd_clk_ctrl;
|
|
a_latch_en <= '1' after Tpd_clk_ctrl;
|
|
b_latch_en <= '1' after Tpd_clk_ctrl;
|
|
--
|
|
pc_out_en1 <= '1' after Tpd_clk_ctrl;
|
|
const2 <= X"0000_0004" after Tpd_clk_const;
|
|
alu_latch_en <= '1' after Tpd_clk_ctrl;
|
|
alu_function <= alu_addu after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi1 = '0';
|
|
a_latch_en <= '0' after Tpd_clk_ctrl;
|
|
b_latch_en <= '0' after Tpd_clk_ctrl;
|
|
alu_latch_en <= '0' after Tpd_clk_ctrl;
|
|
pc_out_en1 <= '0' after Tpd_clk_ctrl;
|
|
const2 <= null after Tpd_clk_const;
|
|
--
|
|
wait until phi2 = '1';
|
|
pc_latch_en <= '1' after Tpd_clk_ctrl;
|
|
--
|
|
wait until phi2 = '0';
|
|
pc_latch_en <= '0' after Tpd_clk_ctrl;
|
|
--
|
|
----------------------------------------------------------------
|
|
-- execute instruction, (EX, MEM, WB)
|
|
----------------------------------------------------------------
|
|
if debug then
|
|
write(L, string'("controller: execute"));
|
|
writeline(output, L);
|
|
end if;
|
|
--
|
|
case IR_opcode is
|
|
when op_special =>
|
|
case IR_sp_func is
|
|
when sp_func_nop =>
|
|
null;
|
|
when sp_func_sequ | sp_func_sneu |
|
|
sp_func_sltu | sp_func_sgtu |
|
|
sp_func_sleu | sp_func_sgeu =>
|
|
do_EX_set_unsigned(immed => false);
|
|
do_WB(IR_Rtype_rd);
|
|
when sp_func_add | sp_func_addu |
|
|
sp_func_sub | sp_func_subu |
|
|
sp_func_and | sp_func_or | sp_func_xor |
|
|
sp_func_sll | sp_func_srl | sp_func_sra =>
|
|
do_EX_arith_logic;
|
|
do_WB(IR_Rtype_rd);
|
|
when sp_func_seq | sp_func_sne |
|
|
sp_func_slt | sp_func_sgt |
|
|
sp_func_sle | sp_func_sge =>
|
|
do_EX_set_signed(immed => false);
|
|
do_WB(IR_Rtype_rd);
|
|
when sp_func_movi2s =>
|
|
assert false
|
|
report "MOVI2S instruction not implemented" severity warning;
|
|
when sp_func_movs2i =>
|
|
assert false
|
|
report "MOVS2I instruction not implemented" severity warning;
|
|
when sp_func_movf =>
|
|
assert false
|
|
report "MOVF instruction not implemented" severity warning;
|
|
when sp_func_movd =>
|
|
assert false
|
|
report "MOVD instruction not implemented" severity warning;
|
|
when sp_func_movfp2i =>
|
|
assert false
|
|
report "MOVFP2I instruction not implemented" severity warning;
|
|
when sp_func_movi2fp =>
|
|
assert false
|
|
report "MOVI2FP instruction not implemented" severity warning;
|
|
when others =>
|
|
assert false
|
|
report "undefined special instruction function" severity error;
|
|
end case;
|
|
when op_fparith =>
|
|
case IR_fp_func is
|
|
when fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf |
|
|
fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd |
|
|
fp_func_mult | fp_func_multu | fp_func_div | fp_func_divu |
|
|
fp_func_cvtf2d | fp_func_cvtf2i | fp_func_cvtd2f |
|
|
fp_func_cvtd2i | fp_func_cvti2f | fp_func_cvti2d |
|
|
fp_func_eqf | fp_func_nef | fp_func_ltf | fp_func_gtf |
|
|
fp_func_lef | fp_func_gef | fp_func_eqd | fp_func_ned |
|
|
fp_func_ltd | fp_func_gtd | fp_func_led | fp_func_ged =>
|
|
assert false
|
|
report "floating point instructions not implemented" severity warning;
|
|
when others =>
|
|
assert false
|
|
report "undefined floating point instruction function" severity error;
|
|
end case;
|
|
when op_j =>
|
|
do_MEM_jump;
|
|
when op_jr =>
|
|
do_MEM_jump_reg;
|
|
when op_jal =>
|
|
do_EX_link;
|
|
do_MEM_jump;
|
|
do_WB(natural_to_bv(link_reg, 5));
|
|
when op_jalr =>
|
|
do_EX_link;
|
|
do_MEM_jump_reg;
|
|
do_WB(natural_to_bv(link_reg, 5));
|
|
when op_beqz | op_bnez =>
|
|
do_EX_branch;
|
|
if branch_taken then
|
|
do_MEM_branch;
|
|
end if;
|
|
when op_bfpt =>
|
|
assert false
|
|
report "BFPT instruction not implemented" severity warning;
|
|
when op_bfpf =>
|
|
assert false
|
|
report "BFPF instruction not implemented" severity warning;
|
|
when op_addi | op_subi |
|
|
op_addui | op_subui |
|
|
op_andi | op_ori | op_xori |
|
|
op_slli | op_srli | op_srai =>
|
|
do_EX_arith_logic_immed;
|
|
do_WB(IR_Itype_rd);
|
|
when op_lhi =>
|
|
do_EX_lhi;
|
|
do_WB(IR_Itype_rd);
|
|
when op_rfe =>
|
|
assert false
|
|
report "RFE instruction not implemented" severity warning;
|
|
when op_trap =>
|
|
assert false
|
|
report "TRAP instruction encountered, execution halted"
|
|
severity note;
|
|
wait until phi1 = '1';
|
|
halt <= '1' after Tpd_clk_ctrl;
|
|
wait until reset = '1';
|
|
exit;
|
|
when op_seqi | op_snei | op_slti |
|
|
op_sgti | op_slei | op_sgei =>
|
|
do_EX_set_signed(immed => true);
|
|
do_WB(IR_Itype_rd);
|
|
when op_lb =>
|
|
assert false
|
|
report "LB instruction not implemented" severity warning;
|
|
when op_lh =>
|
|
assert false
|
|
report "LH instruction not implemented" severity warning;
|
|
when op_lw =>
|
|
do_EX_load_store;
|
|
do_MEM_load;
|
|
exit when reset = '1';
|
|
do_WB(IR_Itype_rd);
|
|
when op_sw =>
|
|
do_EX_load_store;
|
|
do_MEM_store;
|
|
exit when reset = '1';
|
|
when op_lbu =>
|
|
assert false
|
|
report "LBU instruction not implemented" severity warning;
|
|
when op_lhu =>
|
|
assert false
|
|
report "LHU instruction not implemented" severity warning;
|
|
when op_sb =>
|
|
assert false
|
|
report "SB instruction not implemented" severity warning;
|
|
when op_sh =>
|
|
assert false
|
|
report "SH instruction not implemented" severity warning;
|
|
when op_lf =>
|
|
assert false
|
|
report "LF instruction not implemented" severity warning;
|
|
when op_ld =>
|
|
assert false
|
|
report "LD instruction not implemented" severity warning;
|
|
when op_sf =>
|
|
assert false
|
|
report "SF instruction not implemented" severity warning;
|
|
when op_sd =>
|
|
assert false
|
|
report "SD instruction not implemented" severity warning;
|
|
when op_sequi | op_sneui | op_sltui |
|
|
op_sgtui | op_sleui | op_sgeui =>
|
|
do_EX_set_unsigned(immed => true);
|
|
do_WB(IR_Itype_rd);
|
|
when others =>
|
|
assert false
|
|
report "undefined instruction" severity error;
|
|
end case;
|
|
--
|
|
end loop;
|
|
--
|
|
----------------------------------------------------------------
|
|
-- loop exited on reset
|
|
----------------------------------------------------------------
|
|
assert reset = '1'
|
|
report "Internal error: reset code reached with reset = '0'"
|
|
severity failure;
|
|
--
|
|
-- start again
|
|
--
|
|
end process sequencer;
|
|
|
|
|
|
end behaviour;
|