jens
2f7ab91e0d
git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
130 lines
3.0 KiB
VHDL
130 lines
3.0 KiB
VHDL
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-- VHDL Test Bench Created from source file vconfig.vhd -- 20:20:01 05/01/2004
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--
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LIBRARY ieee;
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USE ieee.numeric_std.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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ENTITY vconfig_tb IS
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END vconfig_tb;
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ARCHITECTURE behavior OF vconfig_tb IS
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COMPONENT vconfig
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PORT(
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RES : IN std_logic;
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nINIT_B : IN std_logic;
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CLK : IN std_logic;
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DONE : IN std_logic;
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CCLK : OUT std_logic;
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CCLK_PRESCALER : IN std_logic_vector(5 downto 0);
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LOAD_PRESCALER : in std_logic;
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DIN : IN std_logic_vector(31 downto 0);
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DOUT : OUT std_logic;
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BUF_IS_EMPTY : inout std_logic;
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LOAD_SREG : IN std_logic
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);
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END COMPONENT;
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SIGNAL RES : std_logic := '1';
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SIGNAL nINIT_B : std_logic := '0';
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SIGNAL CLK : std_logic := '0';
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SIGNAL DONE : std_logic := '1';
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SIGNAL CCLK : std_logic;
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SIGNAL CCLK_PRESCALER : std_logic_vector(5 downto 0);
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SIGNAL LOAD_PRESCALER : std_logic := '0';
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SIGNAL DOUT : std_logic;
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SIGNAL DIN : std_logic_vector(31 downto 0);
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SIGNAL LOAD_SREG : std_logic := '0';
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SIGNAL BUF_IS_EMPTY : std_logic;
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constant ClockPeriod : Time := 16.667 ns;
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constant CFG_PRESCALE: integer range 0 to 63 := 2;
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BEGIN
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uut: vconfig PORT MAP(
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RES => RES,
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nINIT_B => nINIT_B,
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CLK => CLK,
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DONE => DONE,
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CCLK => CCLK,
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CCLK_PRESCALER => CCLK_PRESCALER,
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LOAD_PRESCALER => LOAD_PRESCALER,
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DOUT => DOUT,
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DIN => DIN,
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BUF_IS_EMPTY => BUF_IS_EMPTY,
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LOAD_SREG => LOAD_SREG
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);
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busclock: process
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begin
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CLK <= '1';
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loop
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wait for (ClockPeriod / 2);
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CLK <= not CLK;
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end loop;
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end process;
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-- *** Test Bench - User Defined Section ***
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tb : PROCESS
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BEGIN
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wait for 5*ClockPeriod;
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RES <= '0';
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wait for 5*ClockPeriod;
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CCLK_PRESCALER <= CONV_STD_LOGIC_VECTOR(CFG_PRESCALE,6);
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wait for 1.5*ClockPeriod;
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LOAD_PRESCALER <= '1';
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wait for 1*ClockPeriod;
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LOAD_PRESCALER <= '0';
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wait for 1*ClockPeriod;
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DIN <= X"BAA34569";
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wait for 1.5*ClockPeriod;
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LOAD_SREG <= '1';
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wait for 1.0*ClockPeriod;
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LOAD_SREG <= '0';
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wait for 5*ClockPeriod;
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DONE <= '0';
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wait for 2*ClockPeriod;
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nINIT_B <= '1';
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wait for 30.0*real(CFG_PRESCALE)*ClockPeriod*2;
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DIN <= X"8654F41B";
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wait for 1.5*ClockPeriod;
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LOAD_SREG <= '1';
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wait for 2.0*ClockPeriod;
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LOAD_SREG <= '0';
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wait for 29.0*real(CFG_PRESCALE)*ClockPeriod*2;
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DONE <= '1';
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wait for 10.0*ClockPeriod;
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nINIT_B <= '0';
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wait; -- will wait forever
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END PROCESS;
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-- *** End Test Bench - User Defined Section ***
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END;
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