jens
2f7ab91e0d
git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
75 lines
1.6 KiB
VHDL
75 lines
1.6 KiB
VHDL
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-- VHDL Test Bench Created from source file main_top.vhd -- 22:41:27 06/08/2004
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY main_top_main_top_tb_vhd_tb IS
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END main_top_main_top_tb_vhd_tb;
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ARCHITECTURE behavior OF main_top_main_top_tb_vhd_tb IS
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COMPONENT main_top
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PORT(
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res : IN std_logic;
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clki : IN std_logic;
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di : IN std_logic;
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clko : OUT std_logic;
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do : OUT std_logic
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);
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END COMPONENT;
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constant ClockPeriod : Time := 20 ns;
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SIGNAL res : std_logic := '1';
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SIGNAL clki : std_logic;
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SIGNAL clko : std_logic;
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SIGNAL di : std_logic := '0';
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SIGNAL do : std_logic;
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BEGIN
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uut: main_top PORT MAP(
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res => res,
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clki => clki,
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clko => clko,
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di => di,
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do => do
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);
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clkgen: process
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begin
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clki <= '1';
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loop
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wait for (ClockPeriod / 2);
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clki <= not clki;
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end loop;
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end process;
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-- *** Test Bench - User Defined Section ***
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tb : PROCESS
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BEGIN
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res <= '1';
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wait for 5*ClockPeriod;
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res <= '0';
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wait for 5*ClockPeriod;
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di <= '1';
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wait for 14.5*ClockPeriod;
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di <= '0';
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wait; -- will wait forever
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END PROCESS;
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-- *** End Test Bench - User Defined Section ***
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END;
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