jens 2e66c57e0c - moved synthesis relevant files to project ...

git-svn-id: http://moon:8086/svn/vhdl/trunk@1140 cc03376c-175c-47c8-b038-4cd826a8556b

2015-05-21 06:48:46 +00:00

Common

- added unisim sources

2015-05-20 05:48:08 +00:00

lib

- moved synthesis relevant files to project

2015-05-21 06:48:46 +00:00

projects/mips_sys

- fixed bitgen

2015-05-20 23:22:50 +00:00

S

Description

No description provided

23 MiB

Languages

VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%