jens
55ee041c08
git-svn-id: http://moon:8086/svn/vhdl/trunk@1421 cc03376c-175c-47c8-b038-4cd826a8556b
131 lines
3.4 KiB
VHDL
131 lines
3.4 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 17:16:42 13.05.2007
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-- Design Name: tb_mix_cpx
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-- Module Name: tb_mix_cpx.vhd
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-- Project Name: mix_cpx
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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use std.textio.all; -- Imports the standard textio package.
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library work;
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use work.fixed_pkg.all;
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use work.mix_cpx_pkg.all;
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ENTITY syn_mix_cpx IS
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Generic (
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nbits_in : integer := 12;
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nbits_in_frac : integer := 12;
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nbits_out : integer := 12;
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nbits_out_frac : integer := 12;
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has_in_reg : boolean := true;
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has_pipe_reg : boolean := true;
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has_out_reg : boolean := true;
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rounding : boolean := true;
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saturating : boolean := false
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);
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Port
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(
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sys_rst : in std_logic;
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sys_clk : in std_logic;
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sys_in_valid : in std_logic;
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sys_x_re_in : in signed(nbits_in-1 downto 0);
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sys_x_im_in : in signed(nbits_in-1 downto 0);
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sys_y_re_in : in signed(nbits_in-1 downto 0);
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sys_y_im_in : in signed(nbits_in-1 downto 0);
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sys_out_valid : out std_logic;
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sys_z_re_out : out signed(nbits_out-1 downto 0);
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sys_z_im_out : out signed(nbits_out-1 downto 0)
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);
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END syn_mix_cpx;
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ARCHITECTURE behavior OF syn_mix_cpx IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT mix_cpx
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GENERIC
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(
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nbits_in : integer;
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nbits_in_frac : integer;
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nbits_out : integer;
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nbits_out_frac : integer;
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has_in_reg : boolean;
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has_pipe_reg : boolean;
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has_out_reg : boolean;
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rounding : boolean;
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saturating : boolean
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);
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PORT
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(
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srst : in std_logic;
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clk : in std_logic;
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in_valid : in std_logic;
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x_re_in : in sfixed;
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x_im_in : in sfixed;
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y_re_in : in sfixed;
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y_im_in : in sfixed;
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out_valid : out std_logic;
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z_re_out : out sfixed;
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z_im_out : out sfixed
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);
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END COMPONENT;
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--Inputs
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SIGNAL x_re_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
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SIGNAL x_im_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
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SIGNAL y_re_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
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SIGNAL y_im_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
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--Outputs
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SIGNAL z_re_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
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SIGNAL z_im_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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inst_mix_cpx: mix_cpx
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GENERIC MAP
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(
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nbits_in => nbits_in,
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nbits_in_frac => nbits_in_frac,
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nbits_out => nbits_out,
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nbits_out_frac => nbits_out_frac,
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has_in_reg => has_in_reg,
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has_pipe_reg => has_pipe_reg,
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has_out_reg => has_out_reg,
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rounding => rounding,
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saturating => saturating
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)
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PORT MAP
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(
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srst => sys_rst,
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clk => sys_clk,
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in_valid => sys_in_valid,
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x_re_in => x_re_in,
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x_im_in => x_im_in,
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y_re_in => y_re_in,
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y_im_in => y_im_in,
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out_valid => sys_out_valid,
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z_re_out => z_re_out,
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z_im_out => z_im_out
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);
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x_re_in <= sfixed(sys_x_re_in);
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x_im_in <= sfixed(sys_x_im_in);
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y_re_in <= sfixed(sys_y_re_in);
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y_im_in <= sfixed(sys_y_im_in);
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sys_z_re_out <= signed(z_re_out);
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sys_z_im_out <= signed(z_im_out);
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END;
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