jens 26ffec7f49 [UART] ...

- composed uart from uart_tx and uart_rx
- tb_uart tests uart

git-svn-id: http://moon:8086/svn/vhdl/trunk@1354 cc03376c-175c-47c8-b038-4cd826a8556b

2016-12-20 22:46:48 +00:00

..

sim

[UART]

2016-12-20 22:46:48 +00:00

bbfifo_16x8.vhd

Initial import

2008-08-23 08:20:30 +00:00

juart_rx.vhd

[JUART]

2016-12-20 19:09:45 +00:00

juart_tx.vhd

[JUART]

2016-12-20 19:09:45 +00:00

kcuart_rx.vhd

Initial import

2008-08-23 08:20:30 +00:00

kcuart_tx.vhd

Initial import

2008-08-23 08:20:30 +00:00

tb_juart_rx.vhd

[JUART]

2016-12-20 19:09:45 +00:00

tb_juart_tx_rx.vhd

[JUART]

2016-12-20 19:14:21 +00:00

tb_juart_tx.vhd

[JUART]

2016-12-20 19:09:45 +00:00

tb_uart.vhd

[UART]

2016-12-20 22:46:48 +00:00

uart_jtag.vhd

[UART]

2015-05-27 15:59:43 +00:00

uart_rx_xil.vhd

[uart]

2015-05-27 16:28:42 +00:00

uart_rx.vhd

[UART]

2016-12-20 20:36:04 +00:00

uart_sim.vhd

[UART]

2015-05-27 15:59:43 +00:00

uart_tx_xil.vhd

[uart]

2015-05-27 16:28:42 +00:00

uart_tx.vhd

[UART]

2016-12-20 20:36:04 +00:00

uart_types.vhd

[Uart]

2015-05-27 15:50:32 +00:00

uart_wb.vhd

- set TX-half full (S/W depends on it)

2015-05-27 19:05:25 +00:00

uart_xil.vhd

- fixed port map (Xilinx bug)

2015-05-28 05:40:41 +00:00

uart.vhd

[UART]

2016-12-20 22:46:48 +00:00