jens
b06e84a2b7
git-svn-id: http://moon:8086/svn/vhdl/trunk@1419 cc03376c-175c-47c8-b038-4cd826a8556b
99 lines
2.1 KiB
VHDL
99 lines
2.1 KiB
VHDL
-- Hello world program.
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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use std.textio.all; -- Imports the standard textio package.
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-- Defines a design entity, without any ports.
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entity test is
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end test;
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architecture behaviour of test is
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subtype test_range_t is integer range -15 to 16;
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type test_t is array (test_range_t range <>) of std_ulogic;
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type natural_ptr is access natural;
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signal a_s, b_s : integer := 10;
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signal c_s : real := 0.0;
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signal clk_s : std_logic := '0';
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signal res_s : std_logic := '1';
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signal test_s : test_t(2 downto -5);
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begin
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resgen:
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process
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begin
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wait for 10 ns;
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res_s <= not res_s;
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wait;
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end process;
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clkgen:
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process
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variable count : natural_ptr;
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begin
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count := new natural'(10);
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wait for 10 ns;
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if (a_s > 0) then
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clk_s <= not clk_s;
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else
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report "Ende der Simulation" severity note;
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end if;
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end process;
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output_proc:
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process (clk_s, res_s)
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variable l : line;
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variable b_v : integer := 0;
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variable c_v : real := 1.0;
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begin
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if (res_s = '1') then
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write (l, String'("Hello world!"));
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writeline (output, l);
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write (l, String'("High="));
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write (l, test_s'high);
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writeline (output, l);
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write (l, String'("Low="));
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write (l, test_s'low);
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writeline (output, l);
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write (l, String'("Left="));
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write (l, test_s'left);
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writeline (output, l);
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write (l, String'("Right="));
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write (l, test_s'right);
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writeline (output, l);
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write (l, String'("Var="));
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write (l, sin(math_pi_over_4));
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writeline (output, l);
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elsif (rising_edge(clk_s)) then
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write (l, String'("a="));
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write (l, a_s);
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writeline (output, l);
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write (l, String'("b="));
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write (l, b_v);
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writeline (output, l);
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write (l, String'("c="));
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write (l, c_v);
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writeline (output, l);
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a_s <= a_s - 1;
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b_v := b_v + 1;
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c_v := 0.1 * c_v;
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end if;
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b_s <= b_v after 3 ns;
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c_s <= c_v after 3 ns;
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end process;
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end behaviour;
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